Intel CEO Pat Gelsinger has discussed around Intel’s process status, comparisons with TSMC in a recent interview. According to Barron’s report, Gelsinger mentioned in the interview that Intel’s 18A process and TSMC’s N2 process seem comparable, with no significant advantage for either of them.

However, Gelsinger claimed that, ‘But the backside power delivery, everybody says Intel, score.’ He further stated, ‘it gives better area efficiency for silicon, which means lower cost. It gives better power delivery, which means higher performance.’

Gelsinger mentioned that good transistor and great power delivery make 18A a little bit ahead of N2. Besides, TSMC has given a very high-cost envelope, where Intel can fit underneath to be margin accretive.

In fact, not only TSMC and Intel, but also including Samsung, the three semiconductor manufacturing giants are actively positioning themselves in the increasingly competitive field of advanced process technology.

At the recent IEEE International Electron Devices Meeting (IEDM), Intel, TSMC, and Samsung each showcased their CFET (Complementary FET) transistor solutions. The stacked CFET transistor architecture involves stacking two types of transistor -nFETs and pFETs- together, aiming to replace Gate-All-Around (GAA) and become the next-generation transistor design for doubling density.

As reported by IEEE Spectrum, Intel was the first foundry to showcase the CFET solution, publicly unveiling an early version back in 2020. During the conference, Intel introduced one of the simplest circuits manufactured with CFET, focusing on improvements for an inverter.

The CMOS inverter sends the same input voltage to the gates of two-transistor stacked together, generating an output that is logically opposite to the input, and the inverter is completed on a single fin.

Intel also improved the CFET stack’s electrical characteristics by increasing the number of nanosheets per device from two to three, decreasing the separation between the two devices from 50 nm to 30 nm.

According to the current progress, experts, as indicated by IEEE Spectrum, anticipate that the commercialization of CFET technology on a large scale will likely take another 7 to 10 years from now. Before reaching that stage, there are still many preparatory tasks that need to be completed.

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(Photo credit: Intel)

According to a report by TechNews, TSMC’s Arizona-based Fab21, currently in the intensive equipment installation phase, has initiated the construction of a small-scale trial production line. With a small amount of equipment expected from multiple supply chain by the end of 2023, industry sources suggest that Fab21 is planning to commence trial production in the first quarter of 2024.

The reason behind TSMC’s anticipated trial production in the first quarter of 2024 stems from orders from its U.S. clients. Market reports indicate that among Fab21’s U.S. clients, in addition to major players like , NVIDIA CEO Jensen Huang has not ruled out placing orders with Fab21. Furthermore, there are indications that Intel, planning to outsource core computing to TSMC’s N3B process, is likely to place orders to Fab21 in the near future.

However, due to cost considerations, despite the commencement of a small-scale trial production line, the initial capacity increase for Fab21’s 4-nanometer process will not accelerate. This situation is expected to persist into the subsequent second phase of the 3-nanometer production line.

Looking back at TSMC’s progress in Arizona, the company announced the construction of the 12-inch wafer Fab21 in Arizona back in 2020, anticipating the commencement of formal equipment installation in the first quarter of 2024 and official mass production before the end of 2024. The initial phase of Fab21 will produce on the 5-nanometer process, with a monthly production capacity of 20,000 wafers.

TSMC later upgraded the initial processs from 5-nanometer to 4-nanometer. However, due to a shortage of skilled installation workers in the region, TSMC postponed the mass production start date to 2025.

In addition, the second phase of the project is currently slated for mass production in 2026, introducing the 3-nanometer process. The total investment for both phases amounts to $40 billion.

Industry sources also acknowledge that Fab21’s manufacturing costs are high, and its capacity cannot compete with TSMC’s fab in Taiwan, making U.S. client orders primarily a response to U.S. government requirements, with the majority of production still centered in Taiwan.

(Image: TSMC)

As TSMC, Samsung, and Intel compete fiercely in the race for 2nm advanced processes, a new wave of the “battle for crucial equipment” is simultaneously unfolding.

According to South Korean reports, ASML, the leader in semiconductor advanced lithography equipment, plans to manufacture ten equipment capable of producing 2nm chips next year, while aiming to increase its annual production capacity to 20 devices in the coming years.

Intel has secured up to six of the 10, taking the lead, while Samsung is also actively pursuing the procurement of the equipment. TSMC faces significant pressure in this competitive landscape.

South Korean tech media SamMobile has unveiled that as major semiconductor manufacturers announce plans to start producing 2nm chips in 2025, ASML is set to unveil equipment capable of manufacturing chips using the 2nm process in the coming months.

The latest extreme ultraviolet (EUV) lithography equipment is expected to increase the numerical aperture (NA) from 0.33 to 0.55. This enhancement improves the light-collecting capability of the optical system, enabling semiconductor fabs to utilize advanced patterning techniques for the production of 2nm process chips.

ASML is the sole global manufacturer of advanced EUV equipment for processes at 7nm. These equipment are not only expensive, costing several million dollars each, but they also have limited production capacity.

It has led to high demand from major semiconductor manufacturers like Samsung, Intel, and TSMC. Currently, only five chipmakers globally, including TSMC, Samsung, SK Hynix, Intel, and Micron, require EUV equipment, with TSMC accounting for 70% of EUV purchases.

Consequently, Samsung is actively pursuing collaboration and has signed a historic agreement with ASML to jointly invest KRW 1 trillion (approximately USD 755 million) in establishing a research and development facility in South Korea.

This collaboration aims to contribute to the development of Samsung’s 2nm process. Samsung plans to commence the production of 2nm process chips by the end of 2025 after acquiring the 2nm manufacturing equipment.

Samsung Electronics Vice Chairman Kyung Kye-hyun, who heads the Device Solutions Division, emphasized that the new agreement with ASML will assist Samsung in acquiring the next-generation high NA EUV equipment.

Kyung said, “Samsung has secured a priority over the High-NA equipment technology. (From the trip), I believe we created an opportunity for us to optimize the usage of High-NA technology for our production of DRAM memory chips and logic chips in the long term.”

On the Intel front, as part of its IDM 2.0 strategy, it is executing a 5 nodes in four years process development plan. Intel emphasizes that its Intel 20A process is progressing towards volume production readiness as planned, while the Intel 18A process is scheduled to test production phase in the first quarter of next year.

Facing the strong competition from Samsung and Intel, TSMC is not sitting idle. According to reports citing from Financial Times, TSMC has showcased its 2nm prototype test results to major clients like Apple and NVIDIA.

TSMC previously mentioned in its earnings call that it expects the 2nm process to enter mass production as scheduled in 2025. The company’s 2nm backside power rail solution is scheduled for the latter half of 2025, with mass production slated for 2026.

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(Photo credit: ASML)

Following Intel’s move to split its outsourced foundry model, TSMC is gearing up to expand its advanced manufacturing processes in Taiwan, ready to face the competition head-on.

According to China Time’s report, following the equipment first tool-in at the 2nm fab in Baoshan scheduled for April next year, industry sources suggest a high likelihood of the 1.4nm fab being established in the second phase of the Central Taiwan Science Park.

Additionally, TSMC is actively expanding its CoWoS process and considering the construction of its 7th advanced packaging and testing plant in the central region, with Chiayi Science Park and Yunlin actively under consideration.

Semiconductor industry insiders point out that TSMC is beginning to feel the pressure, and this year, founder Morris Chang’s main concern regarding competition has shifted from Samsung to the resurgent Intel.

Starting from the second quarter of next year, Intel, a rival of TSMC, plans to separately disclose financial reports for chip development and Intel Foundry Services (IFS), implementing its internal foundry outsourcing model.

Intel’s move aims to protect the assets and know-how of third-party customers. Coupled with international chip design firms gradually releasing orders to Intel due to diversified supply chain concerns, it shows that Intel’s outsourcing strategy is gradually proving effective.

Intel’s recent successes in foundry processes, including the PowerVia backside power delivery technology, glass substrates and Foveros Direct for advanced packaging.

According to TrendForce’s 3Q23 Ranking of  Global Top10 Foundries by Revenue, Intel’s foundry business has entered the global top 10 for the first time, ranking ninth with the industry’s fastest quarterly growth.

Confronted with growing competition from Intel, TSMC is intensifying its efforts and accelerating the construction of advanced process production capacity. The recent expansion plans are becoming clearer, with the 1.4nm fab likely located in the second phase of the Central Taiwan Science Park, aligning with the ongoing increase in demand for advanced packaging.

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(Photo credit: TSMC)

While TSMC makes promising strides in the 2nm process, slated for mass production in 2025, rivals Samsung and Intel are making headlines with aggressive moves to secure cost-effective deals. This surge in competition for the 2nm process is intensifying.

According to CNA, experts suggest that given the escalating rivalry in the AI chip market, it is paramount to have flawless execution in the process. Despite the recent efforts from Samsung and Intel, TSMC is anticipated to clinch the lion’s share of 2nm orders.

TSMC’s 2nm process is on track for mass production in 2025, with construction underway at its first 2nm fab in the Phase 2 Expansion Area of the Baoshan Site in the Hsinchu Science Park. The tool-in is scheduled for April next year. Simultaneously, TSMC’s Kaohsiung fab is earmarked as a crucial production base for 2nm in the future.

• [News] Samsung’s Discount Strategy Challenges TSMC as the Battle for 2nm Orders Heats Up

Samsung is gearing up for mass production of its 2nm process in 2025 as well. Reports from the Financial Times indicate that, in a bid to secure orders from industry giants like NVIDIA, Samsung is contemplating discounted offerings to challenge TSMC.

Intel, in its bid to reclaim its place in the semiconductor landscape, has set an big target of advancing 5 nodes in four years. Sanjay Natarajan, Senior Vice President at Intel, revealed in a recent interview with Nikkei Asia that the company aims to commence mass production of 2nm chips in 2024, with a commitment to providing reasonably priced products. Additionally, Intel’s 18A process is poised for trial production in the first quarter of 2024.

• [News] Intel, Samsung, TSMC Race in Cutting-Edge Processes

Analysts also share the insights of the competitive landscape among the three major semiconductor players, TSMC, Samsung, and Intel. Arisa Liu, the research fellow and director at the Taiwan Industry Economics Services of Taiwan Institute of Economic Research, notes that TSMC’s 2nm is expected to adopt a gate-all-around (GAA) architecture. In contrast, Samsung has taken an early lead by introducing GAA architecture in its 3nm, aiming to outpace TSMC in the 2nm process after 1 or 2 years of adjustments.

Liu highlights the challenges facing Samsung, noting that the 3nm GAA process has exhibited unstable yields. For example, Qualcomm, a major player in mobile chip, has reverted to TSMC for production. Even with Samsung’s plans for bidding at a reduced price, it is anticipated to face difficulties in denting TSMC’s order share in the short term.

Turning attention to Intel, Liu observes that Intel’s current process technology has advanced to Intel 4 and Intel 3, which do not align with the industry’s 4nm and 3nm processes. In reality, Intel’s progress is closer to 7nm or an enhanced version thereof. Notably, Intel’s 3nm products are still estimated to be outsourced to TSMC, signaling a substantial technology gap.

TSMC’s President, C.C. Wei, has previously outlined the company’s plan to initiate mass production of the 3nm N3P process in the latter half of 2024. Notably, its performance metrics, including power, performance, area (PPA), are expected to surpass Intel’s 18A.

Liu further pointed out the news of TSMC’s clients contemplating additional foundry partners has surfaced recently. This move is primarily seen as an attempt to exert pressure on TSMC and gain negotiating leverage. Given the fierce competition in the AI chip market, it is imperative to control precision in the manufacturing process. As such, TSMC’s 2nm is anticipated to secure a significant majority of orders.

(Image: TSMC)

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