With Tesla teaming up with Intel on the “Terafab” initiative and accelerating its push into chip manufacturing, attention in the market is turning to how TSMC will respond. At today’s earnings call, chairman C.C. Wei acknowledged that both Intel and Tesla remain TSMC customers, while also calling Intel a “formidable competitor” that should not be underestimated.

As reported by Bloomberg, Elon Musk’s Tesla team is actively reaching out to semiconductor industry suppliers for its “Terafab” project. The report cites sources saying Tesla has contacted major equipment makers including Applied Materials, Tokyo Electron, and Lam Research as it lays the groundwork for its planned wafer fab buildout. Separately, TechNews reports that the outreach has also expanded to Taiwan-based equipment suppliers and fab construction service providers.

Meanwhile, the Terafab initiative has also drawn in its chip manufacturing partner Samsung Electronics, though Samsung is said to have suggested that additional capacity from its under-construction Taylor, Texas fab could be allocated to Tesla instead, Bloomberg notes. The report adds that Musk is targeting the start of silicon chip production around 2029, with plans to ramp up output thereafter.

Still, TSMC’s C.C. Wei struck a cautious tone on execution timelines, stressing that there are no shortcuts in the foundry business. He noted that building a new fab typically takes 2–3 years, followed by another 1–2 years for ramp-up. Against that backdrop, he reiterated confidence in TSMC’s positioning, saying the company will continue to pursue every possible business opportunity.

NVIDIA–Samsung LPU Tie-Up Draws Attention

Notably, C.C.Wei also commented on Samsung’s cooperation with NVIDIA, its largest AI accelerator customer, on the production of LPUs, when an analyst asked whether the emergence of a new LPU design could reshape the competitive landscape for TSMC.

C.C. Wei declined to comment on specific customer products, but said TSMC is already working with its customer on next-generation LPU designs. He reiterated confidence in the company’s technology position and added that TSMC will continue to pursue “every piece of business possible.”

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• [News] Tesla AI5 Reportedly Uses SK hynix Memory, Samsung LPDDR5X; Samsung SF2T Process Applied Ahead of AI6
• [News] TSMC Sees 2Q Sales Up 10% QoQ to $40.2B; Margins Rise to 65.5%–67.5%, Capex at Top End of $52–56B

(Photo credit: SpaceX)

TSMC holds its earnings call today, with tightness at its 3nm node coming into focus as the foundry giant outlines new plans to expand N3 capacity. Its Chairman and CEO C.C. Wei says that, historically, TSMC does not add capacity once a node reaches its target level; however, in response to strong AI-driven demand from customers, the company is increasing its capex to expand N3 capacity.

Wei says the company is executing a global capacity plan to support robust multi-year demand for 3-nanometer technologies, which are used across smartphones, HPC, AI (including HBM base dies), automotive, and IoT applications.

In Taiwan, TSMC plans to add a new 3nm fab to its GigaFab cluster in Tainan Science Park, with volume production scheduled for the first half of 2027.

In Arizona, its second fab will also adopt 3nm technologies. Construction has already been completed, and volume production is set to begin in the second half of 2027, as Wei highlights.

In Japan, TSMC plans to deploy 3nm technologies at its second fab, with volume production scheduled for 2028.

Aside from these new fabs, TSMC will continue converting 5nm tools to support 3nm capacity in Taiwan. The company is also focusing on capacity optimization across nodes, including flexible support among N7, N5, and N3, emphasizing that it will maximize support for customers across all platforms amid tight supply.

N2 Ramp Gains Momentum with Long-Term Platform Outlook

As for its N2 capacity expansion plan, Wei notes that the node has already entered high-volume manufacturing in the fourth quarter of 2025 with solid yield performance. N2 is ramping in multiple phases at both the Hsinchu and Kaohsiung sites in Taiwan, as the company prioritizes domestic land to support the rapid ramp of its newest nodes, given the need for close integration with R&D operations. Looking ahead, TSMC expects continued enhancements to the node, including N2P and A16, positioning the N2 family as another large and long-lasting platform for the company.

A14 Takes Shape as TSMC’s Next Leap Forward

Looking ahead to its next-generation technologies, TSMC also highlights its A14 node during the earnings call. Wei notes that A14 technology development is progressing well and remains on track, with volume production scheduled for 2028.

According to Wei, the node will feature a second-generation nanosheet transistor structure, delivering a full-node advancement from N2 with improved performance and power efficiency to meet the growing demand for high-performance, energy-efficient computing. Compared with N2, A14 will deliver a 10% to 15% speed improvement at the same power, or a 25% to 30% reduction in power at the same speed, along with close to a 20% increase in chip density, Wei states.

The company expects A14 and its derivatives to further extend its technology leadership, noting strong customer interest and engagement from both smartphone and HPC applications, Wei adds.

Beyond technology roadmap updates, TSMC also addresses the financial implications of its global expansion strategy. TSMC CFO Wendell Huang states that as overseas fabs come online, they will initially dilute gross margins by around 2% to 3%. As capacity scales, the impact could widen to 3% to 4%. Overall, according to TechNews, TSMC’s overseas expansion strategy has shifted from a focus on cost and efficiency to a dual approach of local-for-local supply and geopolitical risk diversification.

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• [News] TSMC Sees 2Q Sales Up 10% QoQ to $40.2B; Margins Rise to 65.5%–67.5%, Capex at Top End of $52–56B
• [News] TSMC 1Q26 Net Income Soars 58% YoY to NT$572.5B Record, EPS NT$22.08; Gross Margin Beats Forecast at 66.2%

(Photo credit: TSMC)

After posting new high net profit in the first quarter, TSMC management projects 2Q26 revenue to land between $39.0 billion and $40.2 billion, representing a year-over-year increase of approximately 32% and a sequential gain of around 10%. On the profitability front, assuming an exchange rate of US$1 to NT$31.7, the company expects gross profit margins to range between 65.5% and 67.5%, while operating profit margins are anticipated to come in at 56.5% to 58.5%.

According to CFO Wendell Huang, gross margin is expected to improve further in the current quarter, supported by higher utilization and continued cost optimization, although partially diluted by overseas fab expansion. The effective tax rate is projected at around 20% for the quarter and 17%–18% for the full year.

Looking ahead, TSMC expects initial 2nm ramp-up in 2H26 to dilute gross margin by 2–3% for the full year. Overseas fab expansion is also expected to weigh on margins by 2%–3% in the near term, potentially widening to 3%–4% over time. Meanwhile, 3nm margins are projected to exceed corporate average levels in 2H26.

Notably, TSMC notes that its 2026 capital expenditure will focus on 5G, AI, and HPC, with capex expected to come in at the high end of the US$52–56 billion range.

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• [News] TSMC 1Q26 Net Income Soars 58% YoY to NT$572.5B Record, EPS NT$22.08; Gross Margin Beats Forecast at 66.2%

(Photo credit: TSMC)

TSMC today announced consolidated revenue of NT$1,134.10 billion, net income of NT$572.48 billion, and diluted earnings per share of NT$22.08 (US$3.49 per ADR unit) for the first quarter ended March 31, 2026.

As Reuters notes, a net profit above NT$505.7 billion would mark its highest-ever quarterly level and extend its profit streak to nine consecutive quarters, the report adds.

Year-over-year, first quarter revenue increased 35.1%, while net income and diluted EPS both increased 58.3%. Compared to fourth quarter 2025, first quarter results represented an 8.4% increase in revenue and a 13.2% increase in net income. All figures were prepared in accordance with TIFRS on a consolidated basis.

In US dollars, first quarter revenue was $35.90 billion, which increased 40.6% year-over-year and increased 6.4% from the previous quarter.

Gross margin for the quarter stood at 66.2%, with operating margin at 58.1% and net profit margin at 50.5%.

Notably, TSMC’s gross margin climbed to a record 62.3% in 4Q25, before setting another all-time high in 1Q26, surpassing the upper end of its 63%–65% guidance range.

In the first quarter, shipments of 3-nanometer accounted for 25% of total wafer revenue; 5-nanometer accounted for 36%; 7-nanometer accounted for 13%. Advanced technologies, defined as 7-nanometer and more advanced technologies, accounted for 74% of total wafer revenue.

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• [News] TSMC 1Q Profit Seen Up ~50% to Record; Meta–Broadcom AI Chips Reportedly Target 2nm, CoWoS-L in 1H27

(Photo credit: TSMC)

Tesla has announced that its AI5 chip has officially completed tape-out, with additional details now emerging. According to Hankyung, the prototype has been confirmed to be produced on Samsung Electronics’ domestic foundry line. As highlighted by SEDaily, the marking “KR2613” is visible on the prototype, indicating that it was manufactured at Samsung Electronics’ foundry facility in Korea (KR) during the 13th week of 2026, corresponding to late March to early April.

This detail carries particular significance. As noted by SEDaily, Tesla’s core autonomous driving chips had until now been produced almost exclusively by Taiwan’s TSMC. The appearance of this prototype label suggests that Samsung Electronics may be beginning to gain a foothold in the supply chain, potentially signaling early signs of a shift in TSMC’s dominance.

Memory adoption details have also emerged. Hankyung indicates that the chip’s memory is supplied by SK hynix, while Samsung Electronics’ memory plays a broader role across the supply chain. Meanwhile, Newsis reports that Tesla’s AI5 chip is equipped with Samsung’s next-generation low-power memory, LPDDR5X.

As for the manufacturing process, SEDaily reports that Samsung has introduced “SF2T,” a custom foundry process tailored exclusively for Tesla. The company indicated that this customized process, originally under development for the follow-up chip AI6, was applied earlier than planned to AI5, reportedly to create a lock-in effect.

As Hankyung indicates, mass production of AI5 is expected to take place across TSMC’s fabs in Taiwan and Arizona, as well as Samsung Electronics’ Taylor fab in Texas, with full-scale production anticipated around 2027.

Notably, beyond AI5, Tesla has reportedly outlined changes to its future advanced chip roadmap. According to ZDNet, Tesla had initially identified only Samsung Electronics as the manufacturer for its AI6 chip. However, the company has since introduced “AI6.5,” an upgraded version of AI6, and decided to outsource its production to TSMC.

Samsung Gains Momentum in 2nm Push, but Challenges Persist

SEDaily notes that as TSMC faces supply constraints, Samsung is benefiting from the resulting spillover demand. The report also adds that sources indicate Samsung’s 2nm process is believed to have secured roughly a 30% unit cost advantage over TSMC.

While Samsung’s 2nm foundry push appears to be making progress, SEDaily notes that it remains too early for optimism. Although Samsung struggled with low yields during the initial rollout of its 3nm Gate-All-Around (GAA) process, the company has shown improvement at the 2nm node. Yields, which were reportedly below 50% in the second half of last year, have recently climbed above 50%, but are still believed to fall short of levels required for stable profitability.

Read more

• [News] Musk Confirms AI5 Tape-Out, but Wrong TSMC Tag Triggers Social Media Mix-Up
• [News] Samsung 2nm Yields Reportedly at ~55%, Below Mass Production Threshold; Qualcomm May Opt for TSMC

(Photo credit: Samsung)

Ahead of its earnings call later today, TSMC is poised to capture incremental orders from the newly announced Meta Platforms–Broadcom AI chip alliance. According to Commercial Times, the partners are targeting the launch of a self-developed chip based on TSMC’s 2nm process as early as 1H27, paired with the foundry’s CoWoS-L advanced packaging technology.

As reported by Reuters, under an expanded agreement, the social media giant will deploy custom-built AI processors as it accelerates efforts to scale the computing infrastructure. Announced Tuesday, the deal extends the partnership through 2029 and includes an initial commitment exceeding one gigawatt of computing capacity.

Meta Platforms’ first in-house chip under its Training and Inference Accelerator (MTIA) program—the MTIA 300—is already powering its ranking and recommendation systems. According to Reuters, three additional generations are planned through 2027, with later iterations increasingly optimized for inference workloads.

Notably, the Commercial Times reports that Meta’s first 2nm AI accelerator—manufactured by TSMC—is expected to feature a compute die designed by Broadcom and be paired with HBM4 memory. The initial version will adopt TSMC’s CoWoS-L advanced packaging, before migrating the design to SoIC (System on Integrated Chips) in the following year, combining a 2nm compute chip with a 3nm I/O stack, the report suggests.

According to Commercial Times, Meta Platforms introduced its first in-house AI chip, MTIA 100, in 2023, built on TSMC’s 7nm process. Its successor, MTIA 200, moved to the foundry’s 5nm node. Meanwhile, sources cited by Economic Daily News indicate that the MTIA 300 is likely being produced on TSMC’s 3nm or 4nm process.

TSMC’s Earnings Preview

As TSMC is set to release its first-quarter earnings on April 16, Reuters reports the company is on track to deliver a fourth straight quarter of record earnings, with net profit for January–March expected to jump around 50% on the back of surging demand for AI infrastructure.

Analysts cited by Reuters note that demand for TSMC’s 3nm process—critical for AI chip production—as well as its advanced packaging capabilities, continues to outpace available capacity, underscoring persistent supply tightness.

While TSMC already posted a 35% year-on-year surge in first-quarter revenue reported last week, the report suggests the foundry leader is set to report first-quarter net profit of NT$543.3 billion (US$17.23 billion).

A result exceeding NT$505.7 billion would mark the company’s highest-ever quarterly profit and extend its streak to a ninth consecutive quarter of earnings growth, the report adds.

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• [News] Meta’s In-House AI Chip Push: Four New Accelerators Gear Up Amid Memory Crunch by 2027
• [News] NVIDIA’s Rubin Ultra Seen Sticking to Dual-Die Design on Packaging Constraints; TSMC 3nm Demand Intact

(Photo credit: TSMC)

On April 7, San’an Optoelectronics announced that its optical communications segment has achieved notable progress in three key areas: high-speed optical chips, overseas market expansion, and automotive optical communications.

In the high-speed optical chip segment, the company has officially launched its 100G EML chip. The product is compatible with mainstream 800G optical module architectures and features a fully self-developed and vertically integrated design-to-manufacturing process, providing a critical domestically sourced component option for next-generation AI computing networks.

The high-performance optical chip market has long been dominated by a handful of U.S. and Japanese players, with relatively low localization rates in China; San’an’s move is expected to help ease supply-demand imbalances across the supply chain.

Regarding overseas expansion, San’an’s CW laser source products have been verified by leading international customers. The product lineup covers mainstream power specifications of 70mW and 100mW, supporting high-speed optical module applications ranging from 400G to 1.6T.

Amid the automotive intelligence trend, San’an is actively expanding into the automotive optical communications field. As autonomous driving places stringent demands on data transmission bandwidth and reliability, traditional transmission architectures face increasing challenges. In response, the company has developed automotive-grade optical chips capable of operating under harsh conditions and has established strategic partnerships with leading downstream players to jointly advance the commercialization of wide-temperature VCSEL and PD products.

San’an noted that, leveraging its vertically integrated manufacturing capabilities, its high-speed PD products for data center applications have already entered mass production. Meanwhile, the 100G EML, CW laser sources, and automotive optical chips are all ready for volume delivery.

It’s also worth noting that in collaboration with Tsinghua University and China Mobile, San’an has successfully developed a Micro LED light source device with high-speed modulation capability. Test results indicate a 3dB modulation bandwidth exceeding 7 GHz; based on communication models, its NRZ-OOK data transmission rate is expected to surpass 10Gb/s, laying a solid technological foundation for the development of short-reach high-speed optical interconnects and next-generation optical communication systems.

(Photo credit: San’an Optoelectronics )

Musk’s TeraFab initiative has sparked broad industry discussion, and Intel’s decision to join the project has further intensified attention. According to CRN, Intel plans to brief employees in the coming weeks on the “scope and nature” of its involvement in the TeraFab chip manufacturing project, based on a memo sent by CEO Lip-Bu Tan last Friday.

As the report indicates, Intel has disclosed few details about its role in TeraFab. In the memo, Tan described the collaboration as a “strategic alliance” between Intel and Musk’s companies, including SpaceX, xAI, and Tesla, noting that Musk’s ambitions across AI, transportation, communications, robotics, and space travel depend on a reliable supply of chips, making Intel a natural partner. He also reiterated earlier social media remarks that Intel will work closely with these companies to help bring up TeraFab.

Still, the report notes that while Tan told employees Intel “will disclose more broadly the scope and nature of this engagement” in the coming weeks, he did not specify whether the information would be made public.

In addition, Tan said Intel CTO Pushkar Ranade will lead the company’s involvement in TeraFab. The CEO added that he will directly oversee the effort. In the memo, Tan also noted that he has asked Ranade to assemble and engage select technologists across the company to contribute to the project.

Musk announced TeraFab last month, saying it would begin with two advanced chip fabrication plants in Austin, Texas. As Reuters notes, one facility will focus on chips for cars and humanoid robotics, while the other will target chips for AI data centers in space.

Key Unknowns Around Timeline, Cost, and Yield

Despite its ambitious vision, analysts cited in the report note that execution visibility remains limited, as there is no clear timeline for high volume manufacturing, no disclosure on capital intensity or cost per wafer, and no guidance on yield ramp expectations, all of which are critical given the sensitivity of advanced node production.

Meanwhile, the cost of building TeraFab remains substantial. As noted by The Edge Malaysia, analysts estimate that the first phase of construction alone could require up to US$35 billion. Reaching a capacity of 1 terawatt would likely involve constructing as many as 140 foundries comparable in scale to TSMC’s first Arizona fab.

Read more

• [News] Intel Joins Tesla TeraFab, May Provide Design and Manufacturing Strength, Signaling Foundry Momentum
• [News] Musk’s Terafab Vision Raises Questions Over TSMC Impact; Advanced Packaging May be Best Entry Point

(Photo credit: Intel on X)

While Tesla is collaborating with Intel on its ambitious Terafab project, the company has also reached a key milestone in its next-generation AI chip program. According to Tesla CEO Elon Musk on X, the AI5 chip has officially completed tape-out.

As previously reported by TechPowerUp, Tesla opts to split production of its AI5 accelerator between Samsung Electronics and TSMC. Manufacturing would be carried out at Samsung’s Taylor, Texas plant as well as TSMC’s Arizona facility, the report adds.

It is interesting to note that Musk also tagged TSMC and Samsung as he attributed the contribution of both foundries on the post. However, the TSMC mention sparked confusion after he cited an incorrect account for the Taiwanese foundry, creating a brief social media mix-up, as noted by Maeli Business Newspaper.

The report points out that Musk tagged @TaiwanSemi_TSC, an account belonging to a similarly named Taiwanese semiconductor company, rather than TSMC’s official presence.

Maeli further explains that tape-out marks the final stage of chip design, meaning the blueprint has been handed over to a foundry for manufacturing. Mass production is expected to begin in 2027, roughly a year from now, the report adds.

In the same post, Musk also noted that several parallel R&D programs—including the next-generation AI6 chip and the Dojo 3 supercomputer processor—are progressing on schedule.

More Details on AI5

According to TradingKey, citing previous disclosures, a single AI5 chip delivers performance comparable to NVIDIA’s Hopper architecture, while a dual-chip setup approaches Blackwell-level capability, but with significantly lower cost and power consumption.

Positioned as the successor to the AI4, the AI5 chip is set to serve as the core computing backbone for Tesla’s autonomous driving systems and humanoid robotics initiatives, the report notes.

Musk, as per the report, previously said that key metrics of the AI5 chip would improve by around 40x compared with the previous-generation AI4, including 9x more memory and 8x higher compute capacity. It is expected to serve as an optimal inference chip for models with fewer than 250 billion parameters, according to TradingKey.

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• [News] Tesla Reportedly Ramps TeraFab Hiring in Taiwan; TSMC Talent Seen as Primary Target
• [News] Delay at Samsung’s Taylor Reportedly Slips Mass Production to 2027, Raising Concerns for Tesla

(Photo credit: Elon Musk’s X)

As U.S. curbs continue to reshape supply chains, China is accelerating its push for semiconductor self-sufficiency and increasingly sourcing critical chipmaking tools from outside the U.S. According to Nikkei, imports of such equipment from Malaysia and Singapore surged in 2025, surpassing shipments from the U.S.  As the report notes, direct imports from the U.S. fell by more than 34% to around $2 billion, the lowest level since 2017.

The report states that while the Netherlands and Japan remain China’s main external sources of semiconductor manufacturing equipment by shipment origin, imports from the two Southeast Asian countries hit record highs. Shipments from Singapore reached $5.7 billion, up more than 17% year over year, while those from Malaysia totaled $3.4 billion, more than doubling from 2024.

China’s Equipment Sourcing Reportedly Shifts to Southeast Asia

Regarding the increase in China’s chipmaking equipment imports from Malaysia and Singapore, analysts cited in the report say that U.S. toolmakers have been expanding manufacturing capacity in the region to better serve customers outside the U.S. Lam Research is expanding its manufacturing footprint in Malaysia to meet rising equipment demand. Singapore, meanwhile, has become a key overseas hub for U.S. toolmakers, with companies such as Applied Materials and KLA establishing manufacturing operations there.

As the report further notes, the three leading U.S. chip equipment makers generated nearly $19 billion in combined revenue from China in fiscal 2025—well above figures suggested by customs data based on shipment origin—highlighting the effectiveness of their production diversification strategies.

China’s Equipment Landscape: Global Sourcing Meets Local Surge

Still, Japan remains a major source of China’s chipmaking equipment imports. According to the report, cumulative imports from Japan exceeded $42 billion between 2020 and 2025, followed by about $35 billion from the Netherlands. Japan is home to key suppliers such as Tokyo Electron, Screen Semiconductor Solutions, and Ebara, while the Netherlands hosts ASML, the world’s largest chip tool maker, along with ASM and Besi. At the same time, amid U.S. restrictions, China’s domestic chip equipment makers are seeing strong growth in 2025, led by Naura, AMEC, ACM Research, and Piotech.

Looking ahead, the U.S. is reportedly considering new legislation to further tighten China’s access to chipmaking equipment. According to South China Morning Post, lawmakers have proposed the Multilateral Alignment of Technology Controls in Hardware (MATCH Act), which, if enacted, would ban exports of key tools to China, including deep ultraviolet (DUV) immersion lithography systems and cryogenic etching equipment.

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• [News] U.S. Proposes to Tighten China Chip Tool Exports; Targets DUV to Slow SMIC and Peers’ Advanced Node Push
• [News] China’s Domestic Chip Equipment Adoption Beats 2025 Target at 35%, Led by NAURA, AMEC

(Photo credit: Applied Materials)

Amid an AI-driven capex upcycle among memory and logic customers, ASML has raised its 2026 revenue outlook. The Dutch chipmaking tool giant now expects sales to reach €36 billion to €40 billion (US$42–47 billion), up from its previous forecast of €34 billion to €39 billion, with a gross margin between 51% and 53%, according to its press release.

As noted by Bloomberg, to meet surging demand, ASML’s key customers—including TSMC and Samsung Electronics—are ramping up production investments. TSMC in January signaled capital expenditure of up to US$56 billion for this year, while SK hynix has mapped out plans to spend roughly US$8 billion on ASML’s advanced tools under an agreement extending through 2027, the report adds.

In an Investing.com transcript, Christophe Fouquet, CEO of ASML, said both memory—particularly DRAM—and advanced logic customers are continuing to ramp adoption of EUV as well as immersion lithography tools. He added that much of this demand is backed by long-term commitments from their customers’ end clients, in line with recent moves by Samsung Electronics and SK hynix to secure multi-year supply agreements with major cloud service providers.

South Korea Demand Surges as China Weakens

According to CNBC, ASML reported stronger-than-expected first-quarter results, with net sales reaching €8.8 billion (US$10.4 billion), ahead of the €8.5 billion consensus forecast from LSEG. Net profit came in at €2.8 billion, also beating expectations of €2.5 billion. The results landed toward the upper end of the company’s previously guided range of €8.2 billion to €8.9 billion in quarterly revenue, the report suggests.

Notably, ASML saw a sharp increase in South Korea demand, with the region contributing 45% of its Q1 sales, up from 22% in 4Q25. According to SeDaily, Samsung is ramping up lithography capacity through a large-scale equipment order, securing around 20 EUV systems from ASML for sub-10nm advanced process nodes. Including DUV tools, total lithography orders reach roughly 70 units, mainly destined for its Pyeongtaek P5 Line 1 fab, the report adds.

Another South Korean memory giant, SK hynix, will secure EUV lithography equipment from ASML worth approximately 12 trillion won over a two-year period, The Elec reports, adding that the order is understood to cover about 24 EUV systems, based on industry estimates of roughly 500 billion won per unit.

On the other hand, China accounted for just 19% of ASML’s 1Q26 sales, down sharply from 36% in 4Q25.

As noted by Bloomberg, ASML is facing intensifying geopolitical pressure in China—its largest market last year—after U.S. lawmakers earlier this month proposed tighter export controls on all immersion deep ultraviolet (DUV) lithography tools, along with restrictions that would bar engineers from servicing equipment at certain Chinese facilities.

According to TradingView, China accounted for around 33% of ASML’s 2025 sales, but forecast that the contribution would fall to roughly 20% in 2026 amid escalating geopolitical restrictions.

Read more

• [News] SK hynix Commits $8B to ASML EUV Equipment by 2027 in Push for AI Memory Dominance
• [News] ASML Reportedly Demonstrates EUV Light Source That Could Lift Chip Output 50% by 2030

(Photo credit: ASML)

According to TrendForce’s latest memory spot price trend report, in the DRAM segment, most spot sellers held firm on quoted prices ahead of mid-April official pricing announcements. However, weak end-demand and cautious purchasing behavior kept overall trading activity subdued. As a result, the average spot price of mainstream chips (DDR4 1Gx8 3200MT/s) fell slightly by 0.48%. In the NAND flash segment, spot market conditions remained largely similar to last week, with overall transactions continuing to skew conservative. Prices for 512Gb TLC wafers declined by 3.13% this week. Details are as follows:

DRAM Spot Price:

This week’s DRAM spot market experienced subdued performance due to the quarter-end and successive holidays. On the supply side, strategies remained conservative, with most spot sellers holding firm on quoted prices as they were waiting for DRAM suppliers’ official price announcements in mid-April. Only a few sellers sporadically reduced prices to secure cash flow, but procurement demand was lacking. Due to insufficient recovery momentum in end-market consumer demand and buyers maintaining strict cost controls, there was a general unwillingness to build inventory at high price levels. This, in turn, led to an overall passiveness on the demand side and an ongoing contraction in transaction volumes. The average spot price of the mainstream chips (i.e., DDR4 1Gx8 3200MT/s) slightly decreased by 0.48% from US$33.56 last week (April 8) to US$33.40 this week (April 14).

NAND Flash Spot Price:

The spot market performed largely the same to that of last week, where overall transactions are leaning towards the conservative end. Buyers, who are continuously confined by exorbitant prices, are mostly on the fence for now. Sellers, on the other hand, are anticipating an improvement in market status from the increase of contract prices, though some of them have chosen to finalize transactions by compromising on prices due to pressure of funds. There has thus been no significant changes to market dynamics. Spots of 512Gb TLC wafers dropped by 3.13% this week (April 13), arriving at US$21.000.

China may be on the verge of another advanced chip breakthrough. According to South China Morning Post, citing local outlets icrank and Shanghai Morning Post, sources say Chinese startup Dishan Technology has made progress in developing a 2nm AI chip. The company is currently in the prototype verification phase for its first 2nm AI GPU.

Still, as the report notes, Dishan’s chip has not yet reached the tapeout stage. Sources from icrank add that Dishan Technology’s previously stated target—completing pre-tapeout verification by the end of 2025 and achieving mass production in Q1 2026—has been delayed. Based on its current R&D progress, the 2nm AI GPU is now expected to gradually enter commercial deployment between late 2028 and 2029.

Dishan’s GPU Architecture and CUDA Ecosystem Strategy

More details have also emerged, with South China Morning Post noting that the company unveiled the basic design of the GPU last July. It adopts a hybrid FinFET/GAA process along with a chiplet-based heterogeneous architecture, which the company said could deliver around a 40% improvement in energy efficiency compared with its predecessor. Mydrivers adds that the chip is equipped with the company’s in-house developed “Dishan Intelligent Core (DS-Core)” and adopts advanced 2.5D CoWoS-L packaging technology.

Meanwhile, South China Morning Post adds that Dishan plans to enhance its supporting toolchains, including CUDA-compatible compilers, to ensure the new chip can work with NVIDIA’s CUDA ecosystem.

Turning Designs into Chips: The Real Bottlenecks Ahead

Notably, as South China Morning Post points out, while Dishan’s design advances could position it closer to global front runners in AI chip design, it remains to be seen whether the company will be able to secure a domestic foundry capable of turning those designs into commercial products, given China is under strict US export controls on chipmaking equipment.

China currently has the capability to manufacture chips at the 7nm node. According to Reuters, sources say Huali Microelectronics—the contract manufacturing arm of China’s Hua Hong Group—is preparing a 7nm process at its Shanghai facility. If realized, it would make Huali the second Chinese chipmaker capable of producing chips at this node after SMIC, the country’s largest foundry.

In addition, South China Morning Post indicates that Dishan must still navigate several challenges as it moves toward mass production, including yield optimisation, compatibility with EDA tools, and supply chain constraints imposed by the U.S.

Dishan, which was founded in 2021, is said to have its R&D team led by several IEEE Fellows, along with experts from China’s national talent programme. The company focuses on the development of high-performance computing and sensor chips, as noted by South China Morning Post.

Read more

• [News] China Reportedly Targets 80% Chip Self-Sufficiency by 2030, Eyes Domestic 7nm Line and 14nm Production Stability
• [News] China Reportedly Aims to Boost 7nm, 5nm Output Fivefold in Two Years, Driven by SMIC, Hua Hong

(Photo credit: FREEPIK)

As memory giants enter the final stage of HBM4 ramp-up ahead of NVIDIA’s Rubin launch, they are taking diverging approaches. According to Chosun Biz, Samsung is pushing to lift 1c DRAM yields for HBM4 toward 80%, while ZDNet reports that SK hynix is set to cut HBM4 volumes this year by 20–30%.

Chosun Biz notes that Samsung’s yields for HBM4-bound DRAM are still estimated at below 60%, which prompts the company aims to lift yields toward near-mature levels in the second half of the year to strengthen its ability to serve key AI customers, including NVIDIA. The report adds that the threshold for mature mass-production yields is generally seen at around 80%.

However, Chosun Biz notes that despite using the same 1c process, HBM4 DRAM requires extra steps—stacking, advanced packaging, thermal control, and signal integrity tuning—making it far more complex than conventional DRAM. Sources also added that even if chip-level yields improve, overall yields can still drop during final HBM4 assembly.

Another factor driving Samsung’s push to improve HBM4 DRAM yields is process cost pressure. Chosun Biz reports the company aims to outpace SK hynix in HBM4 performance through its advanced DRAM technology, but its heavier reliance on EUV lithography—with more layers than rivals—adds process complexity and cost. Without mature yields, the cost burden is expected to remain high.

Notably, compared with HBM4-bound 1c DRAM, Samsung’s logic dies face relatively lighter cost pressure, supported by its 4nm process operating at higher utilization levels and recent price hikes. According to Financial News, the chip giant has reportedly raised prices for HBM4 logic dies by around 40–50% since early 2026.

SK hynix Cuts HBM4 Outlook on Rubin Delays

On the other hand, SK hynix, the current HBM leader, is set to cut HBM4 shipments by 20–30% from its original target, as NVIDIA’s Rubin rollout is delayed, ZDNet reports, adding that the reduced HBM4 volumes are expected to be offset by increased demand for the prior-generation HBM3E and server DRAM.

ZDNet points SK hynix’s adjustment to the fact that key components of the Rubin platform have yet to be fully optimized. Notably, NVIDIA has set a target for HBM4 data processing speeds at around 11Gbps—well above current industry standards, the report highlights.

TrendForce notes that Rubin’s share of NVIDIA’s high-end GPU shipments is expected to slip from 29% to 22% in 2026. Beyond the time needed for HBM4 validation, the platform still faces hurdles including a shift in network interconnects from CX8 to CX9, rising power consumption, and the need for more advanced liquid cooling optimization.

By contrast, Blackwell—powered by HBM3E—is set to gain momentum, with its shipment share projected to climb from 61% to 71%, according to TrendForce.

However, ZDNet notes that SK hynix’s reduced HBM4 volumes are being redirected to HBM3E and server DRAM such as LPDDR, suggesting total memory demand will hold up. Still, the impact on full-year earnings remains uncertain due to differing margin structures across products, the report adds.

On the other hand, Micron, which is advancing at a slower pace in HBM4 development, could see initial shipment volumes come under pressure due to ongoing qualification and quality approval hurdles, according to Business Post, citing analysts.

However, Micron CEO Sanjay Mehrotra, cited by The Elec, noted that non-HBM margins are currently higher than HBM in the March earnings call, suggesting DDR5 profitability now exceeds that of HBM—potentially making this shift less of a concern than it appears. The U.S. memory giant also projects an eye-catching gross margin of 81% in 3QFY26, up from a record 75% in the previous quarter.

Read more

• [News] Samsung Reportedly Lifts HBM4 Logic Die Prices by 40–50% Amid AI Boom; 4nm at Full Capacity
• [News] SK hynix Reportedly Weighs TSMC 3nm for HBM4E Logic Dies to Gain Edge over Samsung

(Photo credit: SK hynix)

Commercialization of glass substrates is accelerating, with South Korean players and Intel increasingly competing head-on for leadership. According to Global Economic, sources indicate that Intel has laid out a glass substrate roadmap targeting 2030 to secure a technological edge, while Korean firms are ramping up commercialization efforts to prevent Intel from gaining the upper hand in setting industry standards.

As the report notes, the stakes center on control of design standards: if Intel succeeds in establishing them, fabless companies worldwide could be compelled to follow its specifications—potentially posing a significant threat to Korea’s semiconductor ecosystem.

Notably, the significance of glass substrates extends beyond current applications. As the report highlights, their key advantage lies in compatibility with the emerging photonics era, where data is transmitted using light rather than electrical signals.

Korea Moves to Scale First, Challenge Intel on Glass Substrate Standards

South Korean companies are stepping up their efforts. The report notes that, in response to Intel’s push, SKC subsidiary Absolics has taken a strategic step by building the world’s first mass-production facility for glass substrates in Georgia. While Intel remains at the research stage, Absolics aims to move into full-scale production first and secure an early lead in materials standards.

Chosun Biz notes that SKC plans to invest approximately KRW 590 billion, which represents about 60% of the funds raised through a recent paid in capital increase, into Absolics’ product development.

Based on the principle that the first to scale production often sets the standard, Absolics’ Georgia facility is already attracting interest from major Silicon Valley tech companies, Global Economic adds.

Samsung Accelerates Integrated Glass Strategy to Counter Intel’s Push

Meanwhile, Samsung is accelerating its efforts as well. According to Global Economic, Samsung Electronics is advancing the commercialization of glass substrates in collaboration with its affiliate Samsung Electro-Mechanics. Beyond component supply, the company is developing an integrated solution in which chips operate directly on glass substrates to deliver an optimized computing environment. Leveraging its strengths in both memory and foundry, Samsung aims to challenge Intel’s lead and establish a Korea-led glass ecosystem.

Corning Draws Focus in Glass Substrate Race

Still, as noted by Bridge Economy, major technical hurdles remain in glass substrate commercialization, with brittleness the most critical. The market believes leadership in next-generation AI semiconductor packaging will hinge on who can first overcome these challenges. As Bridge Economy indicates, the industry is closely watching Corning, a global optical fiber specialist with deep glass expertise, which signed a $6 billion long-term supply deal with Meta in January and has begun collaborating on AI infrastructure expansion.

Competition in the glass substrate market is also intensifying with China’s entry. According to Chosun Biz, Chinese display maker BOE is among the most active players. The company is operating a pilot production line and has reportedly made progress in TGV technology. With a focus on AI chips, BOE plans to begin mass production as early as this year.

Read more

• [News] SKC Reportedly Channels Over Half of ₩1T Capital Increase Into Absolics to Fast-Track Glass Substrates
• [News] Intel Reportedly Presents First Thick-Core Glass Substrate with EMIB, Targeting AI Data Centers

(Photo credit: Intel)

NVIDIA announced on March 31, 2026 that it has entered a strategic partnership with Marvell and will invest US$2 billion, a move expected to support the development of next-generation AI and optical interconnect technologies. According to TrendForce, the collaboration goes beyond Marvell joining the NVLink Fusion ecosystem, with the two companies set to jointly develop silicon photonics.

TrendForce notes that NVIDIA is integrating optical communications, lasers, silicon photonics, customized XPUs, and scale-up networking into its portfolio, signaling that optical transmission is no longer a next-phase option, but an ongoing upgrade in AI infrastructure.

NVIDIA’s Bet on CPO: From Switches to Full AI Rack Architectures

Based on the scope of the collaboration, NVIDIA is not merely taking a stake in a networking or ASIC company, but is formally integrating Marvell into its NVLink Fusion architecture. As TrendForce notes, Marvell will provide custom XPUs and NVLink Fusion-compatible scale-up networking, while NVIDIA will contribute its Vera CPU, ConnectX NICs, BlueField DPUs, NVLink interconnect, Spectrum-X switches, and rack-scale AI compute. This suggests NVIDIA is pursuing a broader strategy to enable more customized AI infrastructure to be built on its own interconnect frameworks.

Focusing on CPO, the strategic significance of this investment lies in Marvell’s ability to extend CPO beyond switches into the domain of custom AI accelerators. Marvell has previously showcased a CPO architecture tailored for custom AI accelerators, emphasizing its ability to scale XPU connectivity from dozens of units within a single rack to hundreds across multiple racks. Marvell said its silicon photonics technology has been shipped commercially for over eight years. For NVIDIA, this effectively brings the interconnect layer—one of the most likely bottlenecks in future AI rack architectures—into a technology stack under its own architectural control.

NVIDIA Builds a Full Optical Interconnect Stack, Beginning with Lumentum and Coherent

Looking back, NVIDIA had already announced separate US$2 billion investments in Lumentum and Coherent, with the partnerships including access to future capacity for advanced laser components. This reflects a shift in NVIDIA’s approach to optical communications, moving from simply procuring components to securing supply through capital investment and orders. Against this backdrop, TrendForce notes that the investment in Marvell is not an isolated move but part of a broader strategy. Lumentum and Coherent focus on upstream lasers and key optical components, while Marvell adds platform capabilities in custom silicon, optical interconnect, and scale up networking.

In other words, NVIDIA is systematically securing the most critical interconnect assets of the AI era—from components and optical engines to system architecture. According to TrendForce, the true significance of NVIDIA’s investment in Marvell lies in ensuring that, even as CSPs adopt custom XPUs, AI ASICs, and diverse accelerators, these systems will continue to be built on NVIDIA-defined interconnect, switching, and optical communication frameworks. For the supply chain, strategic focus will extend beyond GPU packaging and manufacturing to include silicon photonics, optical engines, optical switches, rack-scale scale-up networking, and overall CPO mass production integration capabilities.

Read more

• [News] Silicon Photonics Race Intensifies as TSMC Targets 2026 COUPE Production, Samsung Eyes 2029 CPO Turnkey
• NVIDIA Compute Architecture Paves the Way for Scale-Up Optical Interconnects; CPO Penetration in AI Data Centers Expected to Rise Steadily, Says TrendForce

(Photo credit: Marvell)

Amid speculation that Apple’s first foldable iPhone could face delays, Huawei has moved early to stake its claim in the next wave of foldables. As Patently Apple notes, Huawei’s move is strategically significant—effectively setting the pace in the wide-format foldable race ahead of both Samsung Electronics and Apple, which are reportedly targeting launches as soon as July and September.

According to GIZMOCHINA, Huawei Pura X Max is already open for pre-orders in China, with an official launch set for April 20 alongside the Pura 90 lineup. Notably, the report suggests the model is rumored to be powered by the Kirin 9030 chipset, which is also expected to appear across the upcoming Pura 90 series.

Patently Apple notes that Huawei’s Pura X Max, billed as the world’s first horizontally “wide” foldable smartphone, signals a clear break from the long-dominant tall, narrow form factor. Closer to a compact tablet like the iPad mini, the device features a widescreen inner display with an approximately 4:3 aspect ratio, the report adds.

GIZMOCHINA suggests that when unfolded, the device is expected to feature a 7.6–7.69-inch screen with a 16:10 aspect ratio, delivering a more tablet-like experience. In comparison, CNET reports the iPhone Ultra is rumored to feature a 5.5-inch outer display that unfolds into a 7.8-inch main screen, with pricing expected to land in the $2,000–$2,500 range.

For more details, Patently Apple reports that Huawei’s official images show a strikingly wide foldable when unfolded, with a near-minimal crease and a triple-camera setup on the rear. The proportions reportedly echo the Google Pixel Fold, which also experimented with a wider internal display.

According to the official listing cited by GIZMOCHINA, Huawei’s Pura X Max will be offered in multiple configurations, including 12GB+256GB, 12GB+512GB, 16GB+512GB (Collector’s Edition), and 16GB+1TB variants. Color options are expected to include black, white, blue, gold, and orange.

However, as Patently Apple notes, the wider display could reduce video letterboxing and enhance immersion, but may also bring trade-offs in added bulk and less comfortable one-handed use.

Meanwhile, with Huawei absent from the U.S. market, American consumers will likely have to wait for what Apple and Samsung Electronics bring to the foldable segment later this year, according to CNET.

Samsung and Apple Foldable Plans

The other two smartphone giants, Samsung Electronics and Apple, are also advancing ambitious foldable strategies. According to Business Korea, Samsung is expected to unveil a wave of next-generation foldables this summer, including the “Galaxy Z Fold8” and a new “Galaxy Z Wide Fold,” with both models reportedly starting at around $1,999.

On the other hand, TrendForce’s latest research on the display industry reveals that the foldable smartphone market is expected to see Apple enter as early as the second half of 2026, drawing significant attention to related technological advancements.

TrendForce estimates that Apple, leveraging its strong brand positioning and consumer anticipation, could capture nearly 20% market share in 2026, compressing the share of competitors such as Samsung Electronics and Huawei to around 30% each.

Read more

• [News] Apple Foldable Supply Chain Takes Shape: Samsung, Foxconn, Chinese Suppliers in Focus
• [News] After Foldables, Are 7-Inch Phones Coming Back? Huawei, vivo Reportedly Eye Bigger Displays

(Photo credit: Huawei)

The U.S.’s lead in AI may be narrowing. According to the latest report from the Stanford Institute for Human-Centered Artificial Intelligence (Stanford HAI), China has reportedly closed the performance gap with the U.S. The report notes that U.S. and Chinese models have traded the lead multiple times since early 2025, with DeepSeek-R1 briefly matching the top U.S. model in February 2025 and Anthropic’s leading model holding just a 2.7% edge by March 2026.

This marks a sharp contrast with previous research. As noted by Chosun Biz, the score gap between top U.S. and Chinese models exceeded 300 points in 2023.

As the Stanford report notes, the U.S. retains an edge in high-impact patents and produced 50 notable models in 2025, compared with China’s 30. Meanwhile, China leads in publication volume, citations, total patent output, and industrial robot installations, while South Korea stands out in innovation density, ranking first globally in AI patents per capita.

In addition, the Standford report also highlights that the U.S. hosts the most AI data centers, more than 10 times that of any other country, even as the U.S.-China AI model performance gap has narrowed.

On the investment front, the report notes that while the U.S. continues to lead in AI investment, its ability to attract global talent is declining. U.S. private AI investment reached $285.9 billion in 2025, more than 23 times China’s $12.4 billion, though focusing solely on private investment may understate China’s total spending given its government-backed funds, the report adds. However, the number of AI researchers and developers moving to the U.S. has fallen by 89% since 2017, including an 80% drop in the past year alone.

Amid the rapid rise of Chinese AI models, U.S. companies are taking action. According to Bloomberg, citing sources, rivals OpenAI, Anthropic PBC, and Alphabet Inc.’s Google have begun collaborating to curb Chinese competitors from extracting outputs from advanced U.S. AI models to gain an edge in the global race. The firms are sharing information through the Frontier Model Forum to detect so-called adversarial distillation attempts that violate their terms of service.

Read more

• [News] Decoding DeepSeek V4: How Huawei’s Ascend 950 PR Is Powering China’s Push to Break CUDA Dependence
• [News] AI Compute Prices Rise Across China: Tencent Joins Alibaba, Baidu in Hikes; Zhipu Raises Prices Again

(Photo credit: FREEPIK)

Read more

• [News] Samsung Pushes Advanced Nodes, Reportedly Targets 1nm by 2030; 2nm Yields Top 60%
• [News] Samsung Foundry Reportedly Expects 30%+ 2nm Order Growth in 2026; 1.4nm Set for 2029

(Photo credit: Samsung)

Memory is not the only segment where Samsung Electronics is pushing price increases amid surging AI demand. According to Financial News, the chip giant has reportedly raised prices for HBM4 logic dies by around 40–50% since early 2026, signaling a broader normalization of pricing across its semiconductor portfolio.

Financial News reports that the chip—manufactured using Samsung Electronics’s 4nm process—serves as the “brain” of HBM4. Against the backdrop of rapidly rising HBM4 shipments, demand for logic dies has surged in tandem, giving Samsung stronger pricing leverage and driving the reported price increases, the report adds.

The trend, according to Financial News, also reflects that key production lines such as 4nm are already running at full capacity, with Samsung foundry’s overall profitability showing a gradual improvement trend.

Foundry Turnaround Expected in 4Q26

DealSite further notes that improving yields and stabilized performance at Samsung’s 4nm node are beginning to materially reflect HBM4’s impact from this year. The company has adopted a 10nm-class 6th-generation (1c) DRAM core die alongside a 4nm FinFET foundry-based base die in its HBM4 architecture, the report suggests, adding that the base die has already started shipping and is expected to contribute to foundry revenue from the second half of 2026.

Meanwhile, HBM4E—built on the same base die process—is also targeting mass production within 2026, according to DealSite.

DealSite further suggests that in the context of expanding captive demand alongside rising Big Tech reference wins, Samsung’s foundry division is accelerating expectations for an earlier-than-expected turnaround in its non-memory business. According to industry sources cited by the report, the foundry unit could swing to profitability as early as Q4 this year, followed by a more pronounced improvement cycle starting next year.

As a result, the broader non-memory segment—which includes System LSI operations such as mobile application processors (APs) and sensor chips—could see operating losses narrow sharply from an estimated KRW 3–4 trillion in 2026 to around KRW 500 billion in 2027, the report notes.

Notably, TrendForce observed that Samsung is not the only foundry benefiting from high utilization for 4nm: TSMC’s 5/4 nm and below capacity is expected to remain fully utilized through the end of the year, while Samsung Foundry has also seen a notable increase in orders for its 5/4 nm-class modes.

TSMC has therefore raised foundry prices across all nodes at 5/4 nm and below for 2026, and with order visibility extending into 2027, further price increases in subsequent years cannot be ruled out. Samsung similarly informed customers in 4Q25 that it would raise prices for its 5/4 nm foundry services, TrendForce adds.

Read more

• [News] Samsung Reportedly Allocates 50%+ of Pyeongtaek Foundry Capacity to HBM4 Base Die; Said to Win OpenAI Deal
• News] Samsung, SK hynix Reportedly Tapped as NVIDIA Rubin HBM4 Suppliers; Shipments Could Start in March

(Photo credit: Samsung)