[News] Intel CEO Indicated Intel’s 18A Slightly Ahead of TSMC’s N2

2023-12-21 Semiconductors editor

Intel CEO Pat Gelsinger has discussed around Intel’s process status, comparisons with TSMC in a recent interview. According to Barron’s report, Gelsinger mentioned in the interview that Intel’s 18A process and TSMC’s N2 process seem comparable, with no significant advantage for either of them.

However, Gelsinger claimed that, ‘But the backside power delivery, everybody says Intel, score.’ He further stated, ‘it gives better area efficiency for silicon, which means lower cost. It gives better power delivery, which means higher performance.’

Gelsinger mentioned that good transistor and great power delivery make 18A a little bit ahead of N2. Besides, TSMC has given a very high-cost envelope, where Intel can fit underneath to be margin accretive.

In fact, not only TSMC and Intel, but also including Samsung, the three semiconductor manufacturing giants are actively positioning themselves in the increasingly competitive field of advanced process technology.

At the recent IEEE International Electron Devices Meeting (IEDM), Intel, TSMC, and Samsung each showcased their CFET (Complementary FET) transistor solutions. The stacked CFET transistor architecture involves stacking two types of transistor -nFETs and pFETs- together, aiming to replace Gate-All-Around (GAA) and become the next-generation transistor design for doubling density.

As reported by IEEE Spectrum, Intel was the first foundry to showcase the CFET solution, publicly unveiling an early version back in 2020. During the conference, Intel introduced one of the simplest circuits manufactured with CFET, focusing on improvements for an inverter.

The CMOS inverter sends the same input voltage to the gates of two-transistor stacked together, generating an output that is logically opposite to the input, and the inverter is completed on a single fin.

Intel also improved the CFET stack’s electrical characteristics by increasing the number of nanosheets per device from two to three, decreasing the separation between the two devices from 50 nm to 30 nm.

According to the current progress, experts, as indicated by IEEE Spectrum, anticipate that the commercialization of CFET technology on a large scale will likely take another 7 to 10 years from now. Before reaching that stage, there are still many preparatory tasks that need to be completed.

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(Photo credit: Intel)

Please note that this article cites information from Barron’s and IEEE Spectrum