According to Economic Daily News, industry insiders said that Vanguard International Semiconductor (VIS) is in talks to acquire land and facilities from AUO’s Singapore plant for its first 12-inch fab. The estimated investment for this project is a substantial US$2 billion. VIS is making a strategic move to specialize in producing advanced chips for the automotive industry.

AUO is scheduled to hold a conference on October 31st, and VIS will follow suit on November 7th. Both companies are currently in a pre-conference quite period and haven’t made any official comments on the recent rumors.

Per reports, AUO has been gradually relocating its equipment from its Singapore plant back to Taiwan. Following a model where AUO sold its L3B fab and related facilities in Hsinchu Science Park, Taiwan, they plan to sell this Singapore plant to VIS. Notably, this Singapore plant is conveniently located just an eight-minute drive away from TSMC’s Singapore plant (SSMC), and the transaction is estimated to be worth over a billion dollars.

The Singapore plant in question was acquired by AUO in 2010, and it specializes in the production of 4.5th generation low-temperature polycrystalline silicon (LTPS) display panels and also has some capacity for AMOLED displays. However, the land use contract for this plant expired during the pandemic. AUO then redirected the plant’s focus towards supporting display production. However, with a decrease in post-pandemic notebook demand, AUO’s strategy in Singapore shifted from manufacturing to establishing itself as a regional service center.

Recent developments show that AUO has begun a significant production line adjustment.  They’re transforming the Longtan Aspire Park in Northern Taiwan into a hub for mass-producing Micro LED technology and integrated automotive display modules. Insiders suggest that AUO’s LTPS production line in the Singapore plant has already started moving to Longtan Aspire Park, where they’re gearing up for Micro LED technology development and eventual mass production.

Regarding AUO’s Singapore plant, the company recently stated that they are conducting a thorough evaluation of the operational efficiency of their various plants worldwide. The production schedule for the Singapore plant extends until early 2024, and they’ll subsequently assess the equipment and assets. The company is in the process of discussing and evaluating the related strategies, and they haven’t made any final decisions yet. AUO’s Singapore plant employs approximately 500 people, and they are committed to following local regulations to safeguard their employees’ rights.

In an earning calls last year, Chairman of VIS, Leuh Fang, revealed that the company already operates five 8-inch fabs. Fab 5 still has the potential for increased wafer production, but due to the challenges of acquiring new 8-inch equipment, establishing a brand-new 12-inch fab in Singapore makes more sense if customer demand necessitates capacity expansion.

This development isn’t entirely surprising, as there’s a precedent for fab transactions between AUO and VIS. In late April 2021, AUO sold its L3B plant in the Hsinchu Science Park, along with its related equipment, to VIS for NT$905 million (pre-tax).
(Image: AUO)

TSMC’s new plant in Kumamoto, Japan, is bustling. With more than a thousand employees hard at work, it is on track to commence mass production in 2024. This venture signifies TSMC’s commitment to meet customer demands and navigate geopolitical challenges by expanding its overseas production capabilities.

According to a report by Economic Daily, industry sources reveal that TSMC’s Kumamoto plant is making significant progress in terms of staffing. In August 2023, Taiwanese engineers arrived in Japan accompanied by their families. Simultaneously, locally recruited engineers have completed training and are being deployed to the Kumamoto plant in preparation for the 2024 production.

Notably, TSMC’s Kumamoto plant has successfully trained its workforce. When combined with local employees, the facility now boasts a workforce exceeding a thousand. For the latest Kumamoto plant updates, TSMC assures to refer to the information shared during the October 3Q23 earning conference.

In the prior conference, TSMC disclosed its construction of a cutting-edge wafer fab in Japan. This fab will employ 12/16 nm and 22/28 nm process technologies. TSMC has hired around 800 local employees, most of whom have gained valuable experience in Taiwan. Equipment installation began this month, and mass production is expected by late 2024 if all goes according to schedule.

TSMC’s Kumamoto plant is strongly supported by the Japanese government, Sony Semiconductor Solutions Corporation, Denso, and other partners. The plant’s total capital expenditure is $8.6 billion, and the Japanese Ministry of Economy, Trade and Industry approved a subsidy of 476 billion yen (about US$3.5 billion) in June, covering around 40% of the total Japanese subsidy amount.

The Japanese government is optimistic about TSMC introducing EUV lithography equipment for advanced process mass production in future plants. To secure TSMC’s expansion of the Kumamoto Plant, the government is intensifying its support, with discussions suggesting subsidies of up to 900 billion yen (about US$6.03 billion). This increase underscores Japan’s commitment to boosting domestic semiconductor production value, aligning with their 2030 goal. Companies like TSC, WAHLEE, and MA-tek are poised to expand in pursuit of this goal.

TSC established Shunkawa Co., Ltd. in Japan in 2022 and opened a Kumamoto office in August this year. TSC plans to closely monitor the evolution of new semiconductor plants and explore expansion opportunities in regions such as Tohoku and Hokkaido. Additionally, WAHLEE, a materials distributor, is actively partnering with original equipment manufacturers and Japanese trading companies to tap into the Japanese market.

(Image: TSMC)

As semiconductor manufacturing processes evolve more gradually, 3D packaging emerges as an effective means of prolonging Moore’s Law and enhancing the computational prowess of ICs. Within the realm of 3D stacking technology, the Interuniversity Microelectronics Centre (imec) based in Belgium categorizes 3D integration technologies into four distinct types, each determined by different partitioning locations within a chip: 3D-SIP, 3D-SIC, 3D-SOC, and 3D-IC. Based on our previous discussion of 3D-SIP and 3D-SIC stacking, this article places a spotlight on the other two technologies: 3D-SOC and 3D-IC.

Related Article: Differences Between 3D-SIP and 3D-SIC: Why Are TSMC, Intel, and Samsung All Actively Involved?

3D-SOC

A System on Chip (SOC) involves the redesign of several different chips, all fabricated using the same manufacturing process, and integrates them onto a single chip. 3D-SOC takes this concept to new heights by stacking multiple SOC chips vertically. The image below illustrates the transformation of a 2D System on Chip (2D-SOC), where circuits are redivided into blocks, and then stacked to form a 3D System on Chip (3D-SOC).

Source: imec

imec’s research team previously published a paper on IEEE, outlining the advantages of 3D-SOC and backside interconnects. This technology aims to achieve the integration of diverse chips in a heterogeneous system. By intelligently partitioning circuits, it significantly reduces power consumption and boosts computational performance. In comparison to the trending chiplet technology, 3D-SOC holds a competitive edge.

Eric Beyne, IMEC’s Vice President of Research and Project Director for 3D System Integration, pointed out, “Chiplets involve separately designed and processed chiplet dies. A well-known example are high-bandwidth memories (HBMs) – stacks of dynamic random access memory (DRAM) chips. This memory stack connects to a processor chip through interface buses, which limit their use to latency-tolerant applications. As such, the chiplet concept will never allow for fast access between logic and first and intermediate level cache memories.”

However, it’s essential to acknowledge that 3D-SOC technology comes with apparent drawbacks, primarily higher research and development costs and a longer development timeline compared to 3D-SIP technology. Nevertheless, as applications like AIGC, AR/VR, 8K, and others continue to drive the need for high-speed computing, chips are relentlessly progressing towards higher efficiency, lower power consumption, and smaller size. In this context, 3D-SOC technology will maintain its place in advanced packaging.

Backside Power Delivery Network (BSPDN)

The technology of Backside Power Delivery Network (BSPDN) represents a pivotal development in semiconductor manufacturing, offering several advantages, including more flexible circuit design, shorter metal wire lengths, and higher chip utilization. After transforming a 2D System on Chip (2D-SOC) into a 3D-SOC through layered stacking, the original back sides of the chips become the outer sides of the 3D-SOC. At this stage, the “freed-up” backside of the chips can be utilized for signal routing or as power lines for transistors, in contrast to traditional processes where wiring and power lines are designed on the front side of the wafer.

In the past, backside chips were merely used as carriers, but BSPDN technology allows for more space to be used for logic wafer design. According to simulation results, the transmission efficiency of backside PDN is seven times higher than traditional front-side PDN. Intel has also announced the introduction of this technology in the 20Å and 18Å processes.

To achieve BSPDN, a dedicated wafer thinning process (reducing it to a few hundred nanometers) is required, along with nanoscale through-silicon vias (nTSV) to connect backside power to the front-side logic chip.

Another key technology for BSPDN is the Buried Power Rail (BPR), a miniaturization technique that embeds wires beneath the transistors, with some inside the silicon substrate and others in shallow trench isolation oxide layers. BPR replaces power lines and ground lines under standard cells in traditional processes and further reduces the width of standard cells, mitigating IR voltage drop issues.

The diagram below illustrates BSPDN, where backside PDN’s metal wiring is connected to Buried Power Rails (BPR), and the backside of the chip (BS) is connected to the front side of the logic chip (FS).

Source: imec

3D-IC

The final category, 3D-IC, employs new 3D sequential technology (S3D) or Monolithic technology to vertically stack n-type and p-type transistors, forming a Complementary Field-Effect Transistor (CFET). This technology enables two transistors to be stacked and integrated into the size of a single transistor. This not only significantly increases transistor density but also simplifies the layout of CMOS logic circuits, enhancing design efficiency. As seen in the diagram below, n-type and p-type transistors are integrated vertically to form a CFET.

Source: imec

Nevertheless, the key challenge lies in how to vertically integrate each minuscule transistor and address heat dissipation issues under high-speed computing. Major manufacturers are still in the development phase, but the technology’s biggest advantage lies in achieving the highest component density and the smallest node width, even without nodes. With the continuous increase in demand for high-speed computing, 3D-IC technology is set to become a focal point in the industry’s development.

3D Stacking Leading the Global Semiconductor Advancement

imec has outlined a roadmap for 3D stacking, aiming to reduce pitch spacings and increase point density within unit areas. However, imec also emphasizes that the development of 3D packaging technologies does not follow a linear timeline, as depicted in the figure above, as there is no single packaging technology that can cater to all requirements.

With the rapid development of applications such as AIGC, AR/VR, 8K, 5G, and others, a significant demand for computing power is expected to persist. To overcome the bottlenecks in semiconductor process technology, countries worldwide are fully engaged in advanced packaging research, and 3D stacking undoubtedly takes the center stage as the elixir for Moore’s Law continuation.

Explore More

• An In-Depth Explanation of Advanced Packaging Technology: CoWoS
• Intel and Samsung Join TSMC in Fierce Advanced Packaging Race
• Continuing Moore’s Law: Advanced Packaging Enters the 3D Stacked CPU/GPU Era
• Understanding Chiplets, SoC, and SiP: Why TSMC, Intel, Samsung Invest?

(Image: Samsung)

In recent developments, Samsung Foundry, a subsidiary of Samsung Electronics, has disclosed that it has initiated discussions with major chip clients, gearing up to provide services utilizing 1.4nm and 2nm processes.

It’s been said that Samsung being ahead in the production of 3nm GAA (gate-all-around) process, yet not as favored by major clients as TSMC. In response to the comment, Ki-tae Jeong, the CTO of Samsung Foundry, had share his insights at Semiconductor Expo 2023 in South Korea.

According to the Chosun Ilboon’s report, Jeong pointed out that in the semiconductor foundry industry, it typically takes approximately 3 years for major clients to make their final purchasing decisions. Samsung is actively engaging with prominent clients, and results may become evident in the coming years. Also, the company is currently discussing future processes such as 2nm and 1.4nm with major clients.

How are advanced semiconductor processes progressing?

Compared to mature processes, advanced processes are better suited for applications that demand high performance and low power consumption. With emerging technologies like AI and high-performance computing driving the industry, the demand for advanced processes continues to rise. Leading semiconductor companies are committed to developing new technologies, with chip advanced processes evolving from 5nm to 4nm and now down to 3nm, while looking ahead to the possibility of reaching 2nm and 1.4nm.

Current progress from major players:

Samsung
Samsung has already commenced mass production of its second-generation 3nm chips and aims to introduce the 2nm process by the end of 2025, with the 1.4nm process expected by the end of 2027.

TSMC
TSMC is planning to start production for N3P in the latter half of 2024, with N3X and the 2nm process set to enter mass production in 2025. TSMC will introduce Gate-all-around FETs (GAAFET) transistors for the first time at the 2nm process node, offering a 15% speed increase at the same power consumption and up to a 30% reduction in power consumption at the same speed, all while increasing chip density by more than 15%.

Intel
Intel is diligently pursuing its “Four Years, Five Nodes” plan. Presently, Intel 7 and Intel 4 are in mass production, and the Intel 3 process is expected to enter the readiness for production stage in the latter half of this year. Subsequently, Intel 20A and 18A processes are planned to enter the readiness for production stage in the first and second halves of 2024, respectively.

Moreover, industry experts believe that in the near term, Intel will focus on the Intel 3 process as its flagship offering in the advanced process semiconductor foundry sector to compete with TSMC, Samsung, and other players.

ASE Holdings conducted an earning conference on October 26th to unveil its Q3 financial results and offer insights into future business prospects. All eyes are on ASE’s progress in CoWoS advanced packaging. Joseph Tung, the Chief Financial Officer (CFO) of ASE, expressed confidence in AI and ongoing investments in advanced packaging, expecting a twofold increase in revenue share for advanced packaging in the coming year.

The market’s attention is keenly focused on wafer bank (a storage system used in semiconductor manufacturing to keep semiconductor wafers on hand for production, helping to streamline the manufacturing process) levels and inventory management. Tung mentioned that wafer bank levels are consistently declining and will further reduce Q4. With consumer electronics and computer clients gearing up to launch new products, inventory levels are expected to be maintained at a certain level. Overall, inventory reduction is nearing completion.

Tung emphasized that the real challenge lies not in inventory reduction but in the timing of the recovery in consumer demands and the impact of inflation. ASE remains cautious in its outlook for the upcoming year.

As for AI-related developments, Tung is optimistic about the expansion of CoWoS advanced packaging capacity through TSMC. ASE is also set to boost its production capacity for advanced packaging to cater to urgent customer demands. Next year, it is expected that revenue in advanced packaging will double. Tung emphasized that the AI era has already arrived and expects AI to extend to more terminal devices over the next few years. ASE has also invested in the development of Co-Packaged Optics (CPO) technology, ready to meet customer demands when the market is prepared.

To seize opportunities in advanced packaging, ASE previously introduced an Integrated Design Ecosystem (IDE) to optimize collaborative design tools through a platform, systematically enhancing advanced packaging architecture. This initiative has the potential to reduce design cycles by approximately 50%.

Tung pointed out that there are signs of a recovery in PC-related chip testing and packaging, and this year’s performance in automotive chip testing and packaging is expected to outperform other segments.

Looking ahead to future market conditions, Tung believes that the global semiconductor industry’s environment in the coming year will be more favorable than the current year.

(Image: ASE)