Differences Between 3D-SIP and 3D-SIC: Why Are TSMC, Intel, and Samsung All Actively Involved?

2023-10-09 Semiconductors editor

As semiconductor fabrication technologies continue to advance, the number of transistors in integrated circuits (ICs) has steadily increased. Initially, ICs contained only tens of transistors, but as technology progressed, ICs integrating hundreds of thousands of transistors enabled the realization of 3D animation. ICs with millions of transistors allowed computers to enter households, and today, ICs with hundreds of billions or even trillions of transistors enable digital technology to connect the entire world, profoundly impacting people’s lives.

Over the past 65 years, semiconductor fabrication processes have rapidly evolved, driven by Moore’s Law, gradually reshaping society. However, in recent years, semiconductor processes have approached physical limits, and the failure of Moore’s Law has been a topic of concern. In response, 3D IC stacking and heterogeneous integration technologies have emerged as promising solutions.

3D Stacking Trends

With the rapid development of applications such as AI, AR/VR, and 8K, a significant demand for computation is expected to continue, particularly driving parallel computing systems capable of handling vast amounts of data in a short time. As semiconductor processes slow down, 3D packaging has become an effective means to extend Moore’s Law and enhance IC computing performance.

3D packaging technology offers numerous advantages over traditional 2D packaging. It enables size reduction, with silicon interposer efficiency exceeding 100%, improved connectivity, reduced parasitic effects, lower power consumption, lower latency, and higher operating frequencies. These advantages, along with various benefits of 3D integration and interconnection technologies, make 3D packaging a development direction pursued by major players in the industry.

imec’s Vision for 3D Technology

In the field of 3D stacking technology, imec (imec, the Belgian Interuniversity Microelectronics Centre) defines four categories of 3D integration solutions: 3D-SIP, 3D-SIC, 3D-SOC, and 3D-IC, each requiring different process solutions and 3D integration techniques. Eric Beyne, VP R&D, Director 3D System Integration Program at imec specifically notes that concerning 3D interconnection technology, the scope of 3D interconnection will extend from stack packaging below 1 millimeter (mm), such as Package-on-Package (POP), to below 100 nanometers (nm) with true 3D ICs using transistor stacking, surpassing an interconnect density of 108/mm².

imec identifies three key elements in 3D integration technology: Through-Silicon Via (TSV), die-to-die and die-to-wafer stacking and interconnection, and wafer-to-wafer bonding technology. Beyne points out that TSV miniaturization technology continues to evolve. However, regarding “interconnect gaps,” as TSVs further shrink, microbump technology may struggle to meet higher interconnection demands, making cu-cu hybrid bonding technology a focus of development.

▲The image shows imec’s 3D interconnect technology roadmap, illustrating that as packaging technology continues to advance, node sizes shrink, and density further increases in 3D packaging. (Source:ISSCC 2021)


System-in-Package (SIP), a form of system-level packaging, connects multiple chips that undergo different fabrication processes and preliminary packaging using heterogeneous integration techniques, integrating them within the same packaging shell. 3D-SIP involves vertically stacking multiple SIP chips, including packaging interconnects, fan-out wafer-level packaging, and solder ball bonding.

▲The image on the left is a schematic diagram of 3D-SIP packaging, where the connection points on both sides of the PCB board link the chips that have undergone initial packaging from top to bottom. The image on the right is an actual product illustration. (Source:TrendTorce (Left),ISSCC 2021(Right))

Currently, the connection pitch in existing solutions is approximately 400 micrometers (µm). imec’s research aims to increase the interconnectivity of such SIPs by 100 times, reducing connection pitch to 40 µm. Common applications of 3D-SIP packaging include RF FEMs, TWS Barbuds SoCs.


The second category, 3D-SIC (Stacking IC), involves the stacking of individual chips on top of each other. 3D-SIC is achieved by stacking chips on an interposer or wafer, with the finished chips bonded to the top of the wafer. Chips are interconnected through TSVs and microbumps, with industry solutions achieving pitch sizes as small as 40 µm. The technology is applied to products like 3D-DRAM and logic chips, connected alongside optical I/O units on the interposer. Currently, 3D-SIC technology is widely used in High-Bandwidth Memory (HBM) manufacturing.

▲The image depicts a schematic diagram of 3D-SIC, which utilizes cu-cu hybrid bonding technology to connect the upper and lower layers of ICs. (Source:imec)

3D stacking packaging is leading the global semiconductor industry, and imec has outlined a development blueprint focused on reducing interconnection pitch and increasing contact density per unit area, positioning 3D stacking as a solution to continue Moore’s Law amid slowing semiconductor processes.

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This article is from TechNews, a collaborative media partner of TrendForce.

(Photo credit: TSMC )