Exploring the Significance of 3D-SOC and 3D-IC in Cutting-Edge 3D Advanced Packaging

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As semiconductor manufacturing processes evolve more gradually, 3D packaging emerges as an effective means of prolonging Moore’s Law and enhancing the computational prowess of ICs. Within the realm of 3D stacking technology, the Interuniversity Microelectronics Centre (imec) based in Belgium categorizes 3D integration technologies into four distinct types, each determined by different partitioning locations within a chip: 3D-SIP, 3D-SIC, 3D-SOC, and 3D-IC. Based on our previous discussion of 3D-SIP and 3D-SIC stacking, this article places a spotlight on the other two technologies: 3D-SOC and 3D-IC.

Related Article: Differences Between 3D-SIP and 3D-SIC: Why Are TSMC, Intel, and Samsung All Actively Involved?

3D-SOC

A System on Chip (SOC) involves the redesign of several different chips, all fabricated using the same manufacturing process, and integrates them onto a single chip. 3D-SOC takes this concept to new heights by stacking multiple SOC chips vertically. The image below illustrates the transformation of a 2D System on Chip (2D-SOC), where circuits are redivided into blocks, and then stacked to form a 3D System on Chip (3D-SOC).

Source: imec

imec’s research team previously published a paper on IEEE, outlining the advantages of 3D-SOC and backside interconnects. This technology aims to achieve the integration of diverse chips in a heterogeneous system. By intelligently partitioning circuits, it significantly reduces power consumption and boosts computational performance. In comparison to the trending chiplet technology, 3D-SOC holds a competitive edge.

Eric Beyne, IMEC’s Vice President of Research and Project Director for 3D System Integration, pointed out, “Chiplets involve separately designed and processed chiplet dies. A well-known example are high-bandwidth memories (HBMs) – stacks of dynamic random access memory (DRAM) chips. This memory stack connects to a processor chip through interface buses, which limit their use to latency-tolerant applications. As such, the chiplet concept will never allow for fast access between logic and first and intermediate level cache memories.”

However, it’s essential to acknowledge that 3D-SOC technology comes with apparent drawbacks, primarily higher research and development costs and a longer development timeline compared to 3D-SIP technology. Nevertheless, as applications like AIGC, AR/VR, 8K, and others continue to drive the need for high-speed computing, chips are relentlessly progressing towards higher efficiency, lower power consumption, and smaller size. In this context, 3D-SOC technology will maintain its place in advanced packaging.

Backside Power Delivery Network (BSPDN)

The technology of Backside Power Delivery Network (BSPDN) represents a pivotal development in semiconductor manufacturing, offering several advantages, including more flexible circuit design, shorter metal wire lengths, and higher chip utilization. After transforming a 2D System on Chip (2D-SOC) into a 3D-SOC through layered stacking, the original back sides of the chips become the outer sides of the 3D-SOC. At this stage, the “freed-up” backside of the chips can be utilized for signal routing or as power lines for transistors, in contrast to traditional processes where wiring and power lines are designed on the front side of the wafer.

In the past, backside chips were merely used as carriers, but BSPDN technology allows for more space to be used for logic wafer design. According to simulation results, the transmission efficiency of backside PDN is seven times higher than traditional front-side PDN. Intel has also announced the introduction of this technology in the 20Å and 18Å processes.

To achieve BSPDN, a dedicated wafer thinning process (reducing it to a few hundred nanometers) is required, along with nanoscale through-silicon vias (nTSV) to connect backside power to the front-side logic chip.

Another key technology for BSPDN is the Buried Power Rail (BPR), a miniaturization technique that embeds wires beneath the transistors, with some inside the silicon substrate and others in shallow trench isolation oxide layers. BPR replaces power lines and ground lines under standard cells in traditional processes and further reduces the width of standard cells, mitigating IR voltage drop issues.

The diagram below illustrates BSPDN, where backside PDN’s metal wiring is connected to Buried Power Rails (BPR), and the backside of the chip (BS) is connected to the front side of the logic chip (FS).

Source: imec

3D-IC

The final category, 3D-IC, employs new 3D sequential technology (S3D) or Monolithic technology to vertically stack n-type and p-type transistors, forming a Complementary Field-Effect Transistor (CFET). This technology enables two transistors to be stacked and integrated into the size of a single transistor. This not only significantly increases transistor density but also simplifies the layout of CMOS logic circuits, enhancing design efficiency. As seen in the diagram below, n-type and p-type transistors are integrated vertically to form a CFET.

Source: imec

Nevertheless, the key challenge lies in how to vertically integrate each minuscule transistor and address heat dissipation issues under high-speed computing. Major manufacturers are still in the development phase, but the technology’s biggest advantage lies in achieving the highest component density and the smallest node width, even without nodes. With the continuous increase in demand for high-speed computing, 3D-IC technology is set to become a focal point in the industry’s development.

3D Stacking Leading the Global Semiconductor Advancement

imec has outlined a roadmap for 3D stacking, aiming to reduce pitch spacings and increase point density within unit areas. However, imec also emphasizes that the development of 3D packaging technologies does not follow a linear timeline, as depicted in the figure above, as there is no single packaging technology that can cater to all requirements.

With the rapid development of applications such as AIGC, AR/VR, 8K, 5G, and others, a significant demand for computing power is expected to persist. To overcome the bottlenecks in semiconductor process technology, countries worldwide are fully engaged in advanced packaging research, and 3D stacking undoubtedly takes the center stage as the elixir for Moore’s Law continuation.

Explore More

• An In-Depth Explanation of Advanced Packaging Technology: CoWoS
• Intel and Samsung Join TSMC in Fierce Advanced Packaging Race
• Continuing Moore’s Law: Advanced Packaging Enters the 3D Stacked CPU/GPU Era
• Understanding Chiplets, SoC, and SiP: Why TSMC, Intel, Samsung Invest?

(Image: Samsung)