According to media reports, in response to the booming demand in the artificial intelligence market, TSMC has altered its Kaohsiung factory plan. Originally scheduled for a 28-nanometer mature process, the factory will now be equipped with a 2-nanometer advanced process, with mass production expected to commence in the latter half of 2025. The official announcement of this factory plan is imminent.

During a investor conference held on July 20th, TSMC refrained from making any comments, citing the current quiet period. As reported by “Central News Agency,” Kaohsiung Mayor Chen Chi-mai expressed the city government’s respect for TSMC and pledged full assistance. However, it is worth noting that the 2-nanometer process requires more funding compared to the 28-nanometer process, and TSMC has already informed the Kaohsiung city government, seeking support in terms of water and power supply.

Official data indicates that TSMC’s 2-nanometer process offers a 10% to 15% performance improvement at the same power consumption or a 20% to 30% reduction in power consumption at the same performance level compared to the 3-nanometer process. The primary production base for the 2-nanometer process will be located in Hsinchu’s Baoshan area, with plans to construct four fabs. The trial production is scheduled for 2024, followed by mass production in the latter half of 2025.

(Photo credit: TSMC)

In the continued sluggish consumer electronics market and amidst the booming era of artificial intelligence, semiconductor manufacturers are actively targeting high-performance chips and intensifying the competition over the 2nm process node.

TSMC, Samsung, and the newcomer Rapidus are all actively positioning themselves in the 2nm chip race. Let’s take a look at the progress of these three enterprises.

TSMC: Roadmap for 3nm and 2nm Unveiled

TSMC believes that, at the same power level, the 2nm (N2) chip speed can increase by 15% compared to N3E, or reduce power consumption by 30%, with a density 1.15 times that of its predecessor.

TSMC’s current roadmap for the 3nm “family” includes N3, N3E, N3P, N3X, and N3 AE. N3 is the basic version, N3E is an improved version with further cost optimization, N3P offers enhanced performance, planned for production in the second half of 2024, N3X focuses on high-performance computing devices, and aims for mass production in 2025. N3 AE, designed for the automotive sector, boasts greater reliability and is expected to help customers shorten their product time-to-market by 2 to 3 years.

As for 2nm, TSMC foresees the N2 process to enter mass production in 2025. Media reports from June this year indicate that TSMC is fully committed and has already commenced pre-production work for 2nm chips. In July, the TSMC supply chain revealed that the company has informed equipment suppliers to start delivering 2nm-related machines in the third quarter of next year.

Samsung Electronics: 2nm Mass Production by 2025

In June this year, Samsung announced its latest foundry technology innovations and business strategies.

Embracing the AI era, Samsung’s semiconductor foundry plans to leverage GAA advanced process technology to provide robust support for AI applications. To achieve this, Samsung unveiled detailed plans and performance levels for 2nm process mass production. They aim to realize the application of 2nm process in the mobile sector by 2025, expanding to HPC and automotive electronics in 2026 and 2027, respectively.

Samsung states that the 2nm process (SF2) offers a 12% performance improvement and 25% power efficiency increase over the 3nm process (SF3), with a 5% reduction in chip area.

Rapidus: 2nm Chip Making Progress

Established in November 2022, Rapidus gained significant attention as eight major Japanese companies, including Sony Group, Toyota Motor, SoftBank, Kioxia, Denso, NTT, NEC and MUFG jointly announced their investment in the company. Just a month after its founding, Rapidus forged a strategic partnership with IBM to jointly develop 2nm chip manufacturing technology.

According to Rapidus’ plans, 2nm chips are set to begin trial production in 2025, with mass production commencing in 2027.

[Update] Intel: Being Ambitious to Start Mass Production Of Its 20A Process in The First Half of 2024

Intel is making a vigorous stride into the semiconductor foundry market, setting its sights on rivals like TSMC and Samsung in the arena of advanced process technologies. Intel’s ambitious road map includes kick-starting mass production of its 20A process in the first half of 2024, followed by an 18A process rollout in 2H24. TrendForce points out, however, Intel has a number of significant hurdles to overcome:

Intel’s longstanding focus on manufacturing CPUs, GPUs, FPGAs, and associated I/O chipsets leaves it short of the specialized processes mastered by other foundries. Therefore, the potential success of Intel’s acquisition of Tower—a move to broaden its product line and market reach—is a matter of crucial importance.

Beyond financial segregation, the division of Intel’s actual manufacturing capabilities poses a pivotal challenge. It remains to be seen whether Intel can emulate the complete separation models like those of AMD/GlobalFoundries or Samsung LSI/Samsung Foundry, staying true to the foundry principle of not competing with clients. Adding complexity to the mix, Intel faces the potential exodus of orders from a key customer—its own design division.

(Photo credit: TSMC)

According to sources cited by Nikkan Kogyo Shimbun, TSMC intends to commence the construction of the second fab in Kikuyo-cho, Kumamoto Prefecture, Japan, in April 2024, with the goal of commencing production before the end of 2026.

It is worth mentioning that news about TSMC’s plan to build its second fab in Japan had already surfaced earlier this year. In January, TSMC’s CEO, CC Wei, revealed that the company was considering establishing a second chip manufacturing facility in Japan. In June, TSMC’s Chairman, Mark Liu, also mentioned during a shareholders’ meeting that the Japanese government expressed a desire for TSMC to continue expanding its investments in Japan, while TSMC was still evaluating the construction of the second fab in the country.

Regarding TSMC’s establishment of a fab in Japan, TrendForce indicated that TSMC has played an instrumental role in fostering the growth of Japan’s semiconductor industry as Japanese fabs are unable to handle manufacturing processes as advanced as 1Xnm. TrendForce posits that TSMC could potentially consider setting up a 7nm production line in Phase 2 of JASM to cater to Japan’s demand for advanced technology. Yet, the ongoing market slowdown necessitates a long-term appraisal before implementing any expansion strategies.

In addition to TSMC, more than 20 new wafer fabs are scheduled for completion in the coming years, despite the industry being in a downturn. According to TrendForce’s statistics report in January this year, there are over 20 planned new wafer fabs worldwide, including 5 in Taiwan, 5 in the United States, 6 in Mainland China, 4 in Europe, and 4 in Japan, South Korea, and Singapore combined.

Furthermore, numerous new wafer fab projects have been announced globally since the beginning of this year. For example, in February, Infineon and Texas Instruments both announced plans to construct new wafer fabs. Infineon plans to invest 5 billion euros to build a 12-inch wafer fab in Germany, while Texas Instruments intends to establish its second 300mm wafer fab in Lehi, Utah, USA. On July 5th, PSMC signed an agreement with SBI of Japan, proposing the establishment of a 12-inch wafer foundry.

Currently, semiconductor resources have become strategic assets. In addition to considering commercial and cost structures, wafer fabs must also account for government subsidy policies, meet customer demands for local production, and maintain supply-demand balance. TrendForce believes that future product diversity and pricing strategies will be key factors for the operation of wafer fabs.

Semiconductor manufacturing leader TSMC held its annual shareholder meeting on June 6, addressing issues including advanced process development, revenue, and capital expenditure. TSMC’s Chairman Mark Liu and President C.C. Wei answered a series of questions. The key points from the industry are summarized as follows:

2023 Capital Expenditure Leaning towards $32 Billion

For TSMC’s Q2 and full-year outlook for this year, the consolidated revenue forecast is between $15.2 and $16 billion, a decrease of 5%-10% from the first quarter. Gross profit margin is expected to range between 52%-54%, and operating profit margin between 39.5%-41.5%. Chairman Mark Liu revealed that this year’s capital expenditure is expected to lean more towards $32 billion.

TSMC’s President C.C. Wei lowered the 2023 growth forecast for the overall semiconductor market (excluding memory), expecting a mid-single digit percentage decrease. The revenue in the wafer manufacturing industry is expected to decrease by a high single digit percentage. At this stage, the overall revenue for 2023 is expected to decrease by a low-to-mid single digit percentage, sliding approximately 1%-6%.

Advanced Process N4P to be Mass Produced this Year

TSMC’s total R&D expenditure for 2022 reached $5.47 billion, which expanded its technical lead and differentiation. The 5-nanometer technology family entered its third year of mass production, contributing 26% to the revenue. The N4 process began mass production in 2022, with plans to introduce the N4P and N4X processes. The N4P process technology R&D is progressing smoothly and is expected to be mass-produced this year. The company’s first high-performance computing (HPC) technology, N4X, will finalize product design for customers this year.

Advanced Packaging Demand Far Exceeds Capacity

Due to the generative AI trend initiated by ChatGPT, the demand for advanced packaging orders for TSMC has increased, forcing an increase in advanced packaging capacity. TSMC also pointed out that the demand for TSMC’s advanced packaging capacity far exceeds the existing capacity, and it is forced to increase production as quickly as possible. Chairman Mark Liu stated that the current investment in R&D focuses on two legs, namely 3D IC (chip stacking) and advanced packaging.

At present, three-quarters of TSMC’s R&D expenditure is used for advanced processes, and one quarter for mature and special processes, with advanced packaging falling under mature and special processes.

(Photo credit: TSMC)

The surge in AIGC and new technologies such IoT, AI, 5G, AR/VR are driving a huge demand for computational power of high-end chips. This has been even outpacing the performance increase offered by the long-standing Moore’s Law, ushering in a “post-Moore” era where revolutions in advanced chip design are crucial.

Over recent years, chiplet design has seemingly become the mainstream approach for upgrading high-end chips. The concept is to allow more transistors on a single chip, effectively increasing the production yield of high-end chips while reducing overall costs.

By the large, major IC players have all jumped on board. Even Apple has joined the game by releasing their M1 Ultra SoC using the chiplet concept, which doubles computational performance by integrating two M1 Max units in a single chip.

The CPU sector is definitely a clear demonstration of this trend:

• AMD took the leap with chiplet design in their 2nd-gen EPYC CPUs, doubling the computing cores from 32 to 64 within two years, while slashing costs by up to half. The company has extended this approach to their 4th-gen EPYC CPUs and even pioneered the GPU Navi 31, the first of its kind to use chiplets.
• Intel started incorporating chiplets into their Lakefield series SoC in 2020. Looking ahead, their upcoming CPUs like the Meteor Lake set for 2023, and Arrow Lake and Lunar Lake scheduled for 2024, will all use chiplet design.

Transition from Bumping to Hybrid Bonding

Our analysis in “Chiplet Design: A Real Game-Changer for Substrates” laid out the comprehensive impact of the evolution of chiplet technology on substrates. In fact, chiplets have already caused a significant disruption to the most advanced semiconductor packaging technologies, necessitating the transition towards advanced 2.5D and 3D packaging technologies.

The bottleneck of advanced packaging lies in the chiplets’ interconnections, with bump and microbump still being the key technology for linking chips and forming I/O joints. These connection densities are hard to enhance, thus limiting the overall chip’s transmission speed. In addition, the more chiplets being stacked, the bigger the chip volume gets. The challenge is how to limit the chip size within a specific range, considering the current technical constraints.

Therefore, copper-to-copper hybrid bonding, also known as DBI (Direct Bond Interconnect), has been emerging as the key technology route that overcomes major hurdles in chiplet integration from the bottom-up.

Unlike bumping technology, hybrid bonding significantly shrinks the I/O joint space. The future transmission demand requires the I/O joint space between chiplets to be less than 10µm. While bumping is limited to around 20µm, hybrid bonding can take this down to an impressive 1µm or even less. This also means more I/O joints can be fitted in the same chip size – even reaching up to millions on a mere 1cm2 chip.

On top of this, hybrid bonding only adds an extra 1-2µm of thickness, compared to the 10-30µm of microbump, thereby helping reduce the thickness of stacked chips.

To put it simply, hybrid bonding can boost transmission efficiency, minimize energy usage with higher density of copper joints, manage chip volume, and even cut down on material costs.

The Race for Advanced Packaging Is Kicking Off

Moving forward, hybrid bonding is set to become the key technology supporting the continuous development of chiplet design and 3D packaging. This has been exemplified by TSMC’s front-end So IC packaging technology which is based on hybrid bonding. This puts AMD, a key customer of TSMC, in a favorable position to get ahead.

From AMD’s roadmap of 3D V-Cache technology, they have stacked SRAM on top of CCX (CPU Complex), and gradually integrated it into Milan-X series, the EPYC server CPUs, and Ryzen series, the consumer-grade CPUs, over the past two years. This has significantly improved performance and power consumption as a whole.

Not to be outdone, this year Intel also launched their Foveros Direct packaging technology, which is also based on hybrid bonding route. Assuming everything proceeds smoothly, we can anticipate the release of CPUs utilizing Foveros Direct technology by 2024.

As we look at the current products, AMD’s hybrid bonding apparently focuses on stacking SRAM and computing units at the moment. However, as CPU leaders deepen their understanding of this technology, the application field is expected to further expand. In other words, the future of hybrid bonding solutions stacking multiple computation units is just around the corner.