Equipment is playing an indispensable role during the wafer manufacturing process. In response to market needs, the global EUV lithography supplier, ASML, has recently taken significant steps.

ASML’s Bold Move: Annual Investment of EUR 100 Million in Berlin Plant

As reported by the German media “Handelsblatt,” the Netherlands-based company ASML plans to invest EUR 100 million (USD 109 million) in 2023, with a similar annual investment in the subsequent years. This investment aims to enhance the production and development capabilities of ASML’s manufacturing plant located in Berlin, Germany.

Reports indicate that ASML’s Berlin plant primarily produced core components of EUV equipment, including wafer clamps, wafer tables, reticle chucks and mirror blocks. ASML acquired this facility, known as “Berliner Glas,” in 2020.

Foundries Actively Pursue EUV equipment

The EUV equipment plays a crucial role in manufacturing, utilizing specific wavelength light for radiation to precisely imprint images on wafers. Currently, the EUV equipment market is highly concentrated, with only a few global companies mastering this technology. Among them, Dutch company ASML stands out as the world’s largest and most advanced EUV company. Additionally, companies like Nikon, Canon, and Shanghai Micro Electronics Equipment (SMEE) are strategically positioning themselves in the EUV sector.

EUV technology, used for exposing semiconductor process, is indispensable due to its high cost, complex processes, and limited supply. ASML is the sole global supplier of EUV. For advanced processes below 7nm, EUV serves as an essential device. Developed over more than 20 years, EUV technology has become the cornerstone of advanced processes, enabling the continuation of Moore’s Law for at least another decade.

As a crucial EUV equipment supplier, ASML is working on a new generation of NA-EUV equipment, where “NA” represents numerical aperture. A higher NA value means a higher achievable resolution, allowing for more transistors on the chip. It is expected that by the year-end, ASML will unveil the world’s first high-NA EUV and deliver it to Intel.

Currently, both TSMC and Samsung utilize EUV equipment for manufacturing, covering TSMC’s 7nm, 5nm, and 3nm processes and Samsung’s EUV Line (7nm, 5nm, and 4nm) located in Hwaseong, Korea, along with the 3nm GAA process.

TSMC’s 2nm process will continue to leverage EUV technology. In a previous announcement in September, TSMC disclosed the acquisition of Intel’s subsidiary IMS for up to US 432.8 million, focusing on the research and production of electron beam lithography machines. Industry experts believe that TSMC’s move ensures the technical development of critical equipment and meets the supply demand for the commercialization of 2nm.

Following 2nm chips. Samsung plans to achieve mass production of 2nm processes in the mobile field by 2025, expanding to HPC and automotive electronics in 2026 and 2027, respectively. According to the report in September, Samsung is gearing up to secure the yield of the next-generation EUV equipment, High-NA, with the prototype expected to launch later this year and official supply next year.

After announcing its return to the foundry business, Intel revealed in October that it has commenced mass production of Intel 4 process nodes using EUV technology. Currently, both Intel 7 and Intel 4 have achieved mass production, and Intel 3 is progressing according to plan, with the goal of completion by the end of 2023.

(Image: ASML)

The growing importance of advanced processes in wafer foundries is evident, propelled by innovations like AI and high-performance computing. While 3nm chips have entered the consumer market, efforts are underway in wafer foundries to advance to 2nm chips. Recent reports suggest progress in 1nm chips, further fueling the competition among wafer foundries.

2nm Chips: Unveiling in 2025

Anticipated by 2025, the race for 2nm chips is in full swing, with major players like TSMC, Samsung, and Rapidus actively pursuing mass production. TSMC plans to implement GAAFET transistors in its 2nm process by 2025, offering a 15% speed boost and up to a 30% reduction in power consumption compared to N3E, all while increasing chip density by over 15%.

Samsung is on a similar trajectory, planning to unveil its 2nm process by the end of 2025. As report by media in October, Samsung Foundry, said on Semiconductor Expo 2023 in South Korea, has already initiated discussions with major clients, expecting decisions in upcoming future.

Rapidus aims for trial production of 2nm chips in 2025, scaling up to mass production by 2027. Reports in September indicated that ASML plans to establish a technical support hub in Hokkaido, Japan in 2024. Approximately 50 engineers will be dispatched to Rapidus’ ongoing construction site for the 2nm plant, assisting in the setup of EUV lithography equipment on the trial production line, and providing support for factory activation, maintenance, and inspections.

When will 1nm chip arrive?

Apart from 2nm, the industry’s attention turns to 1nm-level chips. According to industry plans, mass production of 1nm-level chips is expected between 2027 and 2030.

Nikkei recently reveals collaboration between Japanese chipmaker Rapidus, Tokyo University, and the French technological research organization Leti to develop foundational technology for 1nm IC design. Talent exchange and technical sharing are slated to begin in 2024, aiming to establish a supply system for indispensable 1nm chip products, crucial for enhancing auto driving and AI performance.

On the other hand, collaborations with IBM for 1nm products are also being considered. The computing performance of 1nm products, anticipated to become mainstream in the 2030s, is expected to surpass 2nm by 10-20%.

TSMC and Samsung are also eyeing 1nm chip development. TSMC’s initial plan to build a 1.4nm process wafer fab in Taiwan faced delays after abandoning the original site selection in October. Samsung aims to launch its 1.4nm process by the end of 2027, with improved performance and power consumption through an increased number of nanosheets per transistor, promising enhanced control over current flow and reduced power leakage.

(Image: TSMC)

According to TechNews’ report, Gitae Jeong, Vice President of Samsung Electronics, recently revealed in an interview that the company is set to introduce the SF1.4 (1.4nm) process, expected to enter mass production in 2027.

This announcement intensifies the competition in advanced semiconductor manufacturing, particularly in the development of 2.5D/3D integrated heterogeneous structure packaging among the three major semiconductor foundry giants.

• TSMC: N3P Process Superior to Intel 18A, N2 to Lead Industry’s Advanced Processes

Previously, the semiconductor industry reported challenges with both TSMC and Samsung achieving yields above 60% for their 3nm processes due to undisclosed issues. TSMC’s yield was reported to be only 55%, below the normal yield rate.

However, TSMC’s President, C.C. Wei, expressed optimism, stating that current N3 demand is better than three months ago, contributing to a healthy growth outlook for TSMC in 2024.

Wei also anticipates that TSMC’s 3nm process will contribute a mid-single-digit percentage (4%-6%) to the company’s annual wafer revenue in 2023.

Regarding competition with rival Intel’s 18A process, Wei believes that TSMC’s N3P process offers better performance, power, and area (PPA), alongside improved cost efficiency and technical maturity. Furthermore, TSMC’s upcoming N2 process is expected to be the industry’s most advanced when introduced.

• Intel: Striving for the Fourth Customer for 18A Process Outsourcing Orders

Intel’s CEO, Pat Gelsinger, has revealed that the 18A process has secured orders from three customers and aims to acquire a fourth customer by the end of the year. The advanced 18A process is scheduled to begin production at the end of 2024, with one customer already having made an advance payment. External expectations suggest that the customer could possibly be NVIDIA or Qualcomm.

Intel has stated that Intel 4 and Intel 3 processes are similar, as are Intel 20A and Intel 18A processes. Consequently, Intel’s primary focus will be on offering Intel 3 and Intel 18A to semiconductor foundry customers. Meanwhile, Intel 4 and Intel 20A processes are more likely to be used internally. However, Intel is open to accommodating customer requests if they express interest in adopting these later processes.

• Samsung: Commencing Mass Production of SF2 in 2025, Prioritizing Internal Use

Due to challenges with the three-nanometer (3nm) manufacturing process, there have been reports that Samsung plans to shift directly to the more advanced two-nanometer (2nm) process.

According to Samsung’s Foundry Forum (SFF) plan, they will begin mass production of the 2nm process (SF2) in 2025 for mobile applications, expand to high-performance computing (HPC) applications in 2026, and further extend to the automotive sector and the expected 1.4nm process by 2027.

Similar to Intel, Samsung intends to prioritize the production of its own products using the 2nm process. The 2nm process products will initially be utilized for Samsung’s in-house products rather than external customer products.

• Summary

While TSMC’s N3 series currently enjoys broad support, including N3E, N3X, and N3P process series, the move to 2nm introduces new variables as it adopts a completely new GAAFET architecture. Regardless, whether it’s TSMC’s N2, Intel’s 18A, or Samsung’s SF2, each of them possesses its competitive strengths. The industry is also eagerly anticipating the future developments in advanced semiconductor processes.

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• [News] Progress and Adoption of Advanced Processes by Samsung, Intel, and TSMC

While 2nm advanced semiconductor chips are yet to enter mass production, the battle for equipment among semiconductor foundries is already in full swing.

TSMC, Samsung, and Rapidus Make Their Moves

To ensure the smooth deployment of 2nm process technology, TSMC, Samsung, and Rapidus have all embarked on pursuits in the upstream equipment sector.

TSMC, on September 12th, announced its intention to acquire a 10% stake in IMS Nanofabrication, a subsidiary of Intel, for no more than $432.8 million. IMS specializes in the development and production of electron beam lithography machines, widely used in semiconductor manufacturing, optical component production, MEMS manufacturing, and more. Industry experts believe that TSMC’s acquisition of IMS will ensure the development of critical equipment technology and meet the supply requirements for the commercialization of 2nm.

On the other hand, Samsung previously acquired a 3% stake in ASML, still holding approximately 0.7% of ASML shares. Additionally, Samsung’s collaboration with ASML continues to deepen. Reports suggest that Samsung is preparing to secure production of the next-generation High-NA EUV lithography machine, with the prototype expected to be unveiled later this year and commercial availability in the following year.

As for the semiconductor newcomer, Rapidus, obtaining ASML’s support is essential, given that EUV is a vital technology for mass-producing chips below 5-7nm. The latest reports from Japanese media indicate that ASML will establish a technical support base in Hokkaido, Japan, in 2024 and dispatch about 50 engineers to assist in setting up EUV lithography equipment in Rapidus’ 2nm chip factory’s pilot production line, offering assistance in commissioning, maintenance, and inspection.

The development of the major manufacturers in 2nm will be revealed in 2025

Leading traditional semiconductor foundries TSMC and Samsung, along with the emerging player Rapidus, are all actively positioning themselves in the 2nm chip landscape. So, how are these three companies progressing?

TSMC is targeting the production of N2 technology by 2025. Reports from June indicated that TSMC is fully committed, initiating preliminary preparations for the trial production of 2nm chips. In July, the TSMC supply chain revealed that TSMC had informed equipment suppliers to begin deliveries of 2nm-related machinery starting in the third quarter of the following year. In September, media reports revealed that TSMC had formed a dedicated 2nm task force, aiming to achieve risk production next year and commence mass production by 2025.

In June, Samsung announced its latest foundry technology innovations and business strategies, unveiling detailed plans and performance levels for 2nm process mass production. They plan to apply the 2nm process to mobile applications by 2025, expanding to HPC and automotive electronics in 2026 and 2027, respectively.

According to Rapidus’ plan, trial production of 2nm chips is set to begin in 2025, with mass production slated for 2027. In July, Rapidus President Atsuyoshi Koike stated that operating a trial production line in 2025 and commencing mass production in 2027 is an ambitious goal, but progress is on track. He noted that once the company’s 2nm process products go into mass production, their unit price will be ten times that of current Japanese-produced logic semiconductors.

With this timeline, it appears that the 2nm chips from these three semiconductor giants will first make their debut in 2025. At that time, the competition for advanced 2nm processes is expected to become even more intense.

(Photo credit: TSMC)

According to Taiwan’s Media TechNews, Taiwan Semiconductor Manufacturing Company (TSMC) is actively building its 2-nanometer (2nm) fab, with significant investments in the northern, central, and southern regions of Taiwan. These investments include the Baoshan fab in Hsinchu, the Central Taiwan Science Park fab, and the Nanzi fab in Kaohsiung. However, the latest supply chain reports suggest that the construction progress of the Baoshan fab is slowing down, potentially affecting the original production schedule. Industry sources speculate that mass production may be delayed until 2026.

In response to these rumors, TSMC stated that the factory construction is currently progressing according to the planned schedule.

TSMC had originally planned to construct Fab 20 at the Baoshan Phase 2 site, with a plan for four 12-inch wafer fabs (P1~P4). Risk Production was scheduled for the second half of 2024, followed by mass production in 2025. Currently, the latest progress indicates that the Hsinchu Science Park Administration has initiated public works for the expansion of the Baoshan Phase 2 project, including infrastructure like surrounding roads and wastewater facilities, and is concurrently handing over the land for TSMC to begin construction.

However, based on supply chain reports, the Baoshan fab construction project is slowing down due to subdued semiconductor demand and uncertainties customer adoption. As a result, the originally scheduled mass production in the second half of 2025 may likely be delayed until 2026.

As for the Kaohsiung fab, it is concurrently starting its 2nm construction, with equipment installation operations originally scheduled to begin just one month after the Baoshan fab. It remains uncertain whether the slowdown in the Baoshan fab construction will have a synchronous impact on the Kaohsiung fab. As for the Taichung fab, it has received approval from the Taichung City government, but construction is expected to commence next year. Some media reports suggest that the Central Taiwan Science Park fab may potentially advance to produce at 1.4nm or even 1nm semiconductor nodes.

Externally, there is speculation that TSMC’s 2nm process will employ nanosheet Gate-All-Around (GAA) transistor architecture for the first time, while Samsung has already adopted GAA technology at the 3nm node. Whether this can give Samsung a competitive edge over TSMC remains to be seen. However, due to the high technical complexity, introducing GAA technology in the early stages of development may face significant yield issues.

What is GAA, and how does it differ from the past FinFET technology?

Based on transistor structure, electrons enter from the source and move towards the drain, with their passage controlled by a metal gate (depicted in green). However, as chip miniaturization continues and the line width of the metal gate shrinks, typically below 20 nanometers, electrons may leak, causing electrical leakage and short circuits. This led to the invention of FinFET technology.

(Source: Applied Materials)

FinFET technology involves standing the source and drain regions vertically (depicted in gray), increasing the contact area with the metal gate. This provides strict control over electrons, preventing them from leaking. The vertical structure resembles a fish fin, hence the name “FinFET.”

However, as the technology scales below 3 nanometers, continuing to use FinFET processes may encounter physical limitations, leading to electrical leakage. To address this, fins need to be transitioned from vertical to horizontal, increasing the contact area even further. This results in the concept of “Gate-All-Around Field-Effect Transistor” (GAAFET).

Samsung began researching GAA architecture early and collaborated with IBM and GlobalFoundries to publish related papers in 2017. TSMC is also prepared to employ nanosheet transistor technology when moving to the 2nm node. However, due to the technical challenges of GAA, the development and production timeline may be delayed. Combined with reports of delays in 2nm fab construction, mass production is likely to be postponed until 2026.

TSMC N2 Nanosheet Concept Image. (Source: Screenshot from the video)