Samsung Electronics and Synopsys jointly announced that the former has successfully taped out its first mobile system-on-chip (SoC) with its 3nm gate-all-around (GAA) process. According to Synopsys, Samsung used the Synopsys.ai EDA suite to help with the SoC’s layouts as well as design verification, to enhance its performance.

While it is important that Samsung utilized the Synopsys.ai suite for developing high-performance SoCs, it is also momentous progress as the semiconductor heavyweight finally tapes out its advanced smartphone APs with the node.

The unnamed high-performance mobile SoC from Samsung adopts a universal CPU and GPU architecture, along with various IP modules from Synopsys. The design team not only leveraged the Synopsys.ai EDA suite for fine-tuning designs, but the Synopsys DSO.ai to maximize its output. In addition, Samsung also targeted to achieve higher performance, lower power consumption, and optimized chip area (PPA) by leveraging Synopsys’ Fusion Compiler RTL-to-GDSII solution.

Although Samsung’s foundry has been using the GAA-based SF3E node for chip production over the past two years, it has never been used to produce chips in its own smartphones, nor on other SoCs. So far, the SF3E node has only been utilized for cryptocurrency mining chips, possibly due to the initially low yields of GAAFET nodes.

Though Samsung’s press release only indicates that this SoC has been produced with GAA nodes, and the company possesses more complex SF3 processes in addition to the first generation 3-nanometer SF3E, it is reasonable to speculate that it is SF3 given the timeline.

Kijoon Hong, vice president of SLSI at Samsung Electronics, stated that the company’s long-term collaboration with Synopsys enables leading SoC designs, showcasing the highest performance, power efficiency, and chip area on advanced mobile CPU cores and SoC designs. The tape out represents an important milestone, as it demonstrates how AI-driven solutions can help realize goals. With the help of the most advanced GAA transistor architecture, ultra-high-yield design systems can be established.

This SoC chip achieves a maximum clock speed increase of 300MHz and a 10% reduction in power consumption. Samsung’s SoC development team also utilized techniques such as design partitioning optimization, multi-source clock synthesis (MSCTS), and intelligent routing optimization to reduce signal interference, while other simpler layering methods have also been employed. According to official statements, with the boost of the Synopsys Fusion Compiler, the development process could skip weeks of ‘manual’ design time.”

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(Photo credit: Samsung)

At TSMC’s North America Technology Symposium, per a report from TechNews, the semiconductor giant unveiled its A16 process, designed to accommodate more transistors, enhance computational performance, and reduce power consumption. Of particular interest is the integration of the Super PowerRail architecture and nanosheet transistors in the A16 chip, driving faster and more efficient development of data center processors.

As Moore’s Law progresses, transistors become smaller and denser, with an increasing number of stacked layers. It may require passing through 10 to 20 layers of fstacking to provide power and data signals to the transistors below, leading to increasingly complex networks of interconnections and power lines. When electrical signals travel downward, there is IR voltage drop, resulting in power loss.

In addition to power loss, the space occupied by power supply lines is also a concern. In the later stages of chip manufacturing, complex layout of power supply lines often occupies at least 20% of resources. Solving the problem of signal network and power supply network resource conflicts, and enabling component miniaturization, has become a major challenge for chip designers. The industry, per the report, is beginning to explore the possibility of moving power supply networks to the backside of the chip.

TSMC’s A16 employs a different chip wiring. The wires that deliver power to the transistors will be located beneath the transistors instead of above them, known as backside power delivery.

Source: TSMC

One of the methods to optimize processors is to mitigate IR drop. This phenomenon lowers the voltage received by the transistors, thus lowering performance. A16’s wiring is less prone to voltage drop, and similarly, Intel also introduced backside power delivery in Intel 20A, not only simplifying power distribution but also allowing for denser chip packaging. The goal is to fit more transistors into the processor to enhance computational power.

Transistors consist of four main components: the source, drain, channel, and gate. The source is where current enters the transistor, the drain is where it exits, and the channel and gate orchestrate the movement of electrons.

TSMC’s A16 directly connects the power transmission lines to the source and drain, making it more complex than other backside power delivery methods like Intel’s. However, TSMC states that the decision for a more complex design aims to enhance chip efficiency.

Using the Super PowerRail in A16, TSMC achieves an 10% higher clock speed or a 15% to 20% decrease in power consumption at the same operating voltage (Vdd) compared to N2P. Moreover, the chip density is increased by up to 1.10 times, supporting data center products.

Source: TSMC

A16 also incorporates NanoFlex, a type of nanosheet transistor. NanoFlex provides chip designers with flexible N2 standard components, serving as the fundamental building block for chip design. Components with lower height can save space and offer higher power efficiency, while those with higher height maximize performance.

Optimizing the combination of high and low components in the same design block allows for the adjustment of power consumption, performance, and area to achieve the best balance. This capability combines various transistor types with different power efficiency, speed, and size configurations. Flexibility enables customers to tightly integrate TSMC chips with their requirements, maximizing performance.

TSMC plans to debut NanoFlex in the 2-nanometer process, with mass production scheduled for 2025. A16 is expected to launch in the second half of 2026.

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The surge in memory product prices continues, driven by the AI wave revitalizing the memory market. According to a report from Liberty Times Net, prices of high-performance DRAM are also on the rise. Industry sources cited by the same report have indicated that SK Hynix’s LPDDR5/LPDDR4/DDR5 and other DRAM products will see a comprehensive price hike of 15-20%.

According to a report from Chinese media Wallstreetcn, it has cited industry sources, noting that SK Hynix’s DRAM product prices have been steadily increasing month by month since the fourth quarter of last year, with cumulative increases ranging from approximately 60% to 100%. This upward trend in memory prices is expected to continue until the second half of the year.

On April 25th, SK Hynix announced its first-quarter financial results, with revenue soaring to KRW 12.42 trillion, marking a staggering 144.3% increase compared to the same period last year. Operating profit reached KRW 2.88 trillion, far exceeding market expectations of KRW 1.8 trillion, and achieving the second-highest historical figure for the same period.

Contrasting with the loss of KRW 3.4 trillion in the same period last year, this performance represents a significant turnaround for SK Hynix, signaling a shift from a prolonged period of stagnation to comprehensive recovery.

Looking ahead, SK Hynix expressed optimism, stating that the growing demand for memory driven by AI and the recovery of demand for general DRAM products starting from the second half of this year will contribute to a stable growth trend in the memory market for the rest of the year.

Industry sources cited by the report predict that as demand for high-end products like HBM increases, requiring larger capacity compared to general DRAM products, the increase in output of high-end products will lead to a relative decrease in supply of general DRAM products. Consequently, both suppliers and clients are expected to deplete their inventories.

In line with the trend of growing memory demand for AI applications, SK Hynix has decided to ramp up the production of its HBM3e products, which began global production in March this year, and expand its customer base. Additionally, the company plans to launch its fifth-generation 10-nanometer class (1b) 32Gb DDR5 DRAM products within this year, aiming to strengthen its market leadership in high-capacity DRAM products for servers.

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(Photo credit: SK Hynix)

In a bid to seize the AI PC market opportunity, Apple is set to debut its new iPad Pro on the 7th, featuring its in-house M4 chip. With the momentum of the M4 chip’s strong debut, Apple reportedly plans to revamp its entire Mac lineup. The initial batch of M4 Macs is estimated to hit the market gradually from late this year to early next year.

It’s reported by a report from Commercial Times that Apple’s M4 chip adopts TSMC’s N3E process, aligning with Apple’s plans for a major performance upgrade for Mac, which is expected to boost TSMC’s operations.

Notably, per Wccftech’s previous report, it is rumored that the N3E process is also used for producing products like the A18 Pro, the upcoming Qualcomm Snapdragon 8 Gen 4, and the MediaTek Dimensity 9400, among other major clients’ products.

Apple held an online launch event in Taiwan on May 7th at 10 p.m. Per industry sources cited by the same report, besides introducing accessories like iPad Pro, iPad Air, and Apple Pencil, the event will mark the debut of the M4 self-developed chip, unveiling the computational capabilities of Apple’s first AI tablet.

With major computer brands and chip manufacturers competing to release AI PCs, such as Qualcomm’s Snapdragon X Elite and X Plus, and Intel introducing Core Ultra into various laptop brands, it is imperative for Apple to upgrade the performance of its products. Therefore, the strategy of highlighting AI performance through the M4 chip comes as no surprise.

According to a report by Mark Gurman from Bloomberg, the M4 chip will be integrated across Apple’s entire Mac product line. The first batch of M4 Macs is said to be expected to debut as early as the end of this year, including new iMac models, standard 14-inch MacBook Pro, high-end 14-inch and 16-inch MacBook Pro, and Mac mini. New products for 2025 will also be released gradually, such as updates to the 13-inch and 15-inch MacBook Air in the spring, updates to the Mac Studio in mid-year, and finally updates to the Mac Pro.

The report from Commercial Times has claimed that the M4 chip will come in three versions: Donan, Brava, and Hidra. The Donan variant is intended for entry-level MacBook Pro, MacBook Air, and low-end Mac mini models. The Brava version is expected to be used in high-end MacBook Pro and Mac mini models, while the Hidra version will be integrated into desktop Mac Pro computers.

Apple’s plan to introduce the M4 chip into its Mac series is expected to boost the revenue of TSMC’s 3-nanometer family. The report has indicated that the M4 chip will still be manufactured using TSMC’s 3-nanometer process, but with enhancements to the neural processing engine (NPU), providing AI capabilities to Apple’s product line. Additionally, industry sources cited by the same report have revealed that the M4 will utilize TSMC’s N3E process, an improvement over the previous N3B process used in the M3 series chips.

Meanwhile, TSMC continues to advance its existing advanced process node optimization versions. Among them, the N3E variant of the 3-nanometer family, which entered mass production in the fourth quarter of last year, will be followed by N3P and N3X. Currently, N3E is highly likely to be featured in the new generation iPad Pro.

Source: TSMC

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(Photo credit: Apple)

With the flourishing of AI applications, two major AI giants, NVIDIA and AMD, are fully committed to the high-performance computing (HPC) market. It’s reported by the Economic Daily News that they have secured TSMC’s advanced packaging capacity for CoWoS and SoIC packaging through this year and the next, bolstering TSMC’s AI-related business orders.

TSMC holds a highly positive outlook on the momentum brought by AI-related applications. During the April earnings call, CEO C.C. Wei revised the visibility of AI orders and their revenue contribution, extending the visibility from the original expectation of 2027 to 2028.

TSMC anticipates that revenue contribution from server AI processors will more than double this year, accounting for a low-teens percentage of the company’s total revenue in 2024. It also expects a 50% compound annual growth rate for server AI processors over the next five years, with these processors projected to contribute over 20% to TSMC’s revenue by 2028.

Per the industry sources cited by the same report from Economic Daily News, they have indicated that the strong demand for AI has led to a fierce competition among the four global cloud service giants, including Amazon AWS, Microsoft, Google, and Meta, to bolster their AI server arsenal. This has resulted in a supply shortage for AI chips from major manufacturers like NVIDIA and AMD.

Consequently, these companies have heavily invested in TSMC’s advanced process and packaging capabilities to meet the substantial order demands from cloud service providers. TSMC’s advanced packaging capacity, including CoWoS and SoIC, for 2024 and 2025 has been fully booked.

To address the massive demand from customers, TSMC is actively expanding its advanced packaging capacity. Industry sources cited by the report have estimated that by the end of this year, TSMC’s CoWoS monthly capacity could reach between 45,000 to 50,000 units, representing a significant increase from the 15,000 units in 2023. By the end of 2025, CoWoS monthly capacity is expected to reach a new peak of 50,000 units.

Regarding SoIC, it is anticipated that the monthly capacity by the end of this year could reach five to six thousand units, representing a multiple-fold increase from the 2,000 units at the end of 2023. Furthermore, by the end of 2025, the monthly capacity is expected to surge to a scale of 10,000 units.

It is understood that NVIDIA’s mainstay H100 chip currently in mass production utilizes TSMC’s 4-nanometer process and adopts CoWoS advanced packaging. Additionally, it supplies customers with SK Hynix’s High Bandwidth Memory (HBM) in a 2.5D packaging form.

As for NVIDIA’s next-generation Blackwell architecture AI chips, including the B100, B200, and the GB200 with Grace CPU, although they also utilize TSMC’s 4-nanometer process, they are produced using an enhanced version known as N4P. The production for the B100, per a previous report from TechNews, is slated for the fourth quarter of this year, with mass production expected in the first half of next year.

Additionally, they are equipped with higher-capacity and updated specifications of HBM3e high-bandwidth memory. Consequently, their computational capabilities will see a multiple-fold increase compared to the H100 series.

On the other hand, AMD’s MI300 series AI accelerators are manufactured using TSMC’s 5-nanometer and 6-nanometer processes. Unlike NVIDIA, AMD adopts TSMC’s SoIC advanced packaging to vertically integrate CPU and GPU dies before employing CoWoS advanced packaging with HBM. Hence, the production process involves an additional step of advanced packaging complexity with the SoIC process.

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(Photo credit: TSMC)