TSMC reported its Q4 2023 financial results, disclosing consolidated revenue of NT$625.53 billion, net income of NT$238.71 billion, and diluted earnings per share of NT$9.21 (US$1.44 per ADR unit). The figures show a flat year-over-year performance in revenue, with a 19.3% decrease in net income and diluted EPS. However, compared to Q3 2023, Q4 demonstrated a robust 14.4% increase in revenue and a 13.1% rise in net income. All financials adhere to TIFRS on a consolidated basis.

In US dollars, Q4 revenue amounted to $19.62 billion, marking a 1.5% YoY decrease but a significant 13.6% increase from the preceding quarter. Key margins for the quarter include a gross margin of 53.0%, operating margin of 41.6%, and a net profit margin of 38.2%.

Notably, in Q4, 3-nanometer shipments constituted 15% of total wafer revenue, 5-nanometer accounted for 35%, and 7-nanometer contributed 17%. Advanced technologies, encompassing 7-nanometer and beyond, comprised 67% of total wafer revenue, highlighting TSMC’s commitment to cutting-edge semiconductor production.

Outlook for 2024: Anticipating a 6.2% Q1 Revenue Decline and Gross Margin of 52-54%; Full-Year Revenue Estimated to Grow 21% to 26%

TSMC foresees a approximately 6.2% quarter-on-quarter decline in revenue for the first quarter of 2024, with President CC Wei expressing optimism for healthy growth throughout the year. The full-year revenue growth is projected to surpass the 20% benchmark in the semiconductor foundry industry, ranging between 21% and 26%.

TSMC CFO Wendell Huang noted that the demand for high-performance computing remains robust. However, due to seasonal factors of the smartphone industry, Q1 2024 revenue is estimated to be around $18 billion to $18.8 billion, representing a 6.2% decline when calculated at the midpoint. The gross margin is anticipated to be approximately 52% to 54%, maintaining a level comparable to the fourth quarter of the previous year, while the operating profit margin is expected to be around 40% to 42%.

CC Wei stated that the semiconductor industry’s revenue, excluding memory, is expected to grow by 10% this year. Foundry industry revenue is also projected to grow by 20%. Leveraging its leading process technology, TSMC anticipates its revenue growth in 2024 to outpace the industry standard, ranging from 21% to 26%.

Regarding the 3-nanometer manufacturing process, CC Wei mentioned that mass production has commenced in the second half of 2023, contributing approximately 6% to the annual revenue. With the impetus from smartphone and high-performance computing demands, the revenue share of the 3-nanometer process is expected to increase to 15% in 2024.

Capital Expenditure: A 16% Decrease in 2023, Estimated to Fall to $28-32 Billion in 2024

TSMC disclosed a total capital expenditure of $30.45 billion for the full year of 2023, a 16.1% decrease from the $36.29 billion spent in 2022. TSMC projects capital expenditures for 2024 to range between $28 billion and $32 billion.

(Image: TSMC)

In the surge of AI advancements, a CoWoS expansion wave is rapidly underway, with TSMC showcasing ongoing ambitions in advanced packaging.

According to Monet DJ, recent industry reports suggest that TSMC is revising upward its capacity plans for SoIC (System-on-Integrated-Chips). By the end of this year, monthly production capacity is expected to jump from around 2,000 units in late 2023 to 5,000-6,000 units, addressing robust demand in the future for AI and HPC.

TSMC’s SoIC represents an industry-first high-density 3D chip stacking technology. Through the Chip on Wafer (CoW) packaging technique, it enables heterogeneous integration of chips with different sizes, functions, and nodes. Production has commenced at its advanced backend Fab 6 in Zhunan.

Quoting industry sources, Money DJ reports that SoIC’s monthly capacity was initially set to expand to 3,000-4,000 units this year from 2,000 units at the end of last year. However, it is now revised upward to 5,000-6,000 units, with a goal to double the capacity by 2025.

CoWoS, a mature technology with 15 years of development, is estimated to reach a monthly capacity of 30,000-34,000 units by the end of this year. TSMC is banking on its globally dominant 3D stacking technology with SoIC. The debut of major customer AMD MI300 utilizing SoIC with CoWoS is seen as pivotal. If successful, AMD could dominate the AI server sector, making TSMC’s SoIC a significant achievement.

Furthermore, Apple, TSMC’s largest customer, is reportedly keenly interested in SoIC. It is said to adopt SoIC with Hybrid Molding technology, currently in small-scale trial production and expected to enter mass production in 2025-2026. The plan is to apply it in products like Mac and iPad, offering cost advantages over current solutions.

As for another major customer of TSMC’s advanced packaging, NVIDIA, although high-end products currently favor CoWoS packaging, the industry anticipates the future integration of SoIC technology.

(Image: TSMC)

TSMC has achieved a breakthrough in next-generation MRAM memory-related technology, collaborating with the Industrial Technology Research Institute (ITRI) to develop a spin-orbit-torque magnetic random-access memory (SOT-MRAM) array chip

This SOT-MRAM array chip showcases an innovative computing in memory architecture and boasts a power consumption of merely one percent of a spin-transfer torque magnetic random-access memory (STT-MRAM) product.

According to a report by the Economic Daily News, industry sources suggest that with the advent of the AI and 5G era, applications such as autonomous driving, precise medical diagnostics, and satellite image recognition require a new generation of memory that is faster, more stable, and has lower power consumption. MRAM, which utilizes common refined magnetic materials found in hard drives, meets the demands of this new generation of memory, attracting major players like Samsung, Intel, and TSMC to invest in research and development.

In the past, MRAM was mainly applied in automotive and base station. However, due to the characteristics of MRAM architecture, it was challenging to achieve a balance between data retention, write endurance, and write speed. A few years ago, a new architecture called Spin-Transfer Torque MRAM (STT-MRAM) emerged, addressing the aforementioned challenges and entering commercialization.

TSMC has successfully developed related MRAM product lines with 22-nanometer, 16/12-nanometer processes and secured orders in markets such as memory and automotive, seizing the MRAM business opportunity.

In a recent development, TSMC, riding on its success, collaborates with the Industrial Technology Research Institute (ITRI) to create an SOT-MRAM array chip, complemented by an innovative computing architecture.

Their collaborative efforts have resulted in a research paper on this microelectronic component, which was jointly presented at the 2023 IEEE International Electron Devices Meeting (IEDM 2023), underscoring the cutting-edge nature of their findings and their pivotal role in advancing next-generation memory technologies.

Dr. Shih-Chieh Chang, General Director of Electronic and Optoelectronic System Research Laboratories at ITRI, highlighted the collaborative achievements of both organizations.

“Following the co-authored papers presented at the Symposium on VLSI Technology and Circuits last year, we have further co-developed a SOT-MRAM unit cell,” said Chang. “This unit cell achieves simultaneous low power consumption and high-speed operation, reaching speeds as rapid as 10 nanoseconds. And its overall computing performance can be further enhanced when integrated with computing in memory circuit design. Looking ahead, this technology holds the potential for applications in high-performance computing (HPC), artificial intelligence (AI), automotive chips, and more.”

(Image: ITRI)

China, Taiwan, and South Korea’s foundry price war continues to heat up. Rumors of price reductions are circulating in the foundry industry, Chinese foundries allegedly lowering their tape out prices, attracting Taiwanese IC design companies to switch their orders.

Companies including Samsung, GlobalFoundries, UMC, and PSMC have reportedly seen customers cancel orders in favor of these Chinese foundries.

According to reports from IJIWEI, China’s SMIC, Huahong Group, and Nexchip began lowering their foundry service prices to Taiwanese IC design companies last year to secure new orders. Many Taiwanese IC design companies have been enticed by these lower prices, prompting them to shift their orders to Chinese foundries. As a result, companies like Samsung, GlobalFoundries, UMC, and PSMC have witnessed customers canceling orders in favor of Chinese manufacturers.

Due to the mature manufacturing processes in China, unaffected by US export restrictions, the lowered wafer fabrication costs have become attractive to Taiwanese IC design companies seeking to enhance their cost competitiveness.

Reports also indicate that this competitive pressure has forced Taiwan’s foundries, UMC and PSMC, to follow suit by reducing their prices. UMC has lowered its 12-inch wafer foundry services by an average of 10-15%, while its 8-inch wafer services have seen an average price reduction of 20%. These price adjustments took effect in the fourth quarter of 2023.

Earlier reports from TechNews had already highlighted that, due to the sluggish semiconductor market conditions in 2023, both China and South Korea aggressively reduced prices to secure orders, with price reductions of up to 20-30% observed in 8-inch and 12-inch mature processes. Taiwanese foundries also made concessions in terms of pricing.

Taiwan’s leading foundry, TSMC, had already initiated pricing concessions in 2023, mainly related to mask costs rather than wafer fabrication. It was reported that these concessions primarily applied to the 7nm process and were dependent on order volumes.

Samsung Foundry, which had previously remained inactive, also adopted a price reduction strategy in the first quarter of this year, offering discounts ranging from 5-15% and indicating a willingness to negotiate.

Looking at the global semiconductor foundry landscape, data released by TrendForce in 2023 showed that Taiwan accounted for approximately 46% of the world’s wafer fabrication capacity, followed by China at 26%, South Korea at 12%, the United States at 6%, and Japan at 2%. However, due to active efforts by China, the United States, and other countries to increase their local capacity shares, by 2027, Taiwan and South Korea’s capacity shares are expected to converge to approximately 41% and 10%, respectively.

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• [News] Competing with TSMC? Samsung Foundry Follows Price Cuts, Offering Discounts Up to 15%

The global foundry advanced process battle is reigniting, as reported by the Commercial Times. TSMC’s 2-nanometer process at the Baoshan P1 wafer fab in Hsinchu is set to commence equipment installation as early as April, incorporating a new Gate-All-Around (GAA) transistor architecture and aiming for mass production in 2025.

Additionally, expansion plans for Baoshan P2 and the Kaohsiung fab are projected to join in 2025, with evaluations underway for Phase 2 in the Central Taiwan Science Park. The competition with Samsung and Intel in the most advanced process is intensifying.

Semiconductor industry sources note the ongoing progress in global foundry advanced processes, with Samsung entering GAA architecture early at 3 nanometers, though facing yield challenges, while Intel anticipates mass production of its RibbonFET architecture at 20A this year.

In response to fierce competition, TSMC must accelerate its pace. The ‘Gate-All-Around’ (GAA) technology is a critical factor determining whether chip processing power will double within 1.5 to 2 years.

As per the report, Samsung’s attempt to lead in the 3-nanometer chip segment, transitioning from traditional FinFET, has faced stability issues in yield, hampering customer adoption, and giving TSMC confidence in its 3-nanometer progress. This also highlights the increased complexity in transitioning from 2D to 3D chip designs with GAA transistor architecture.

Furthermore, Intel is intensifying its efforts to catch up, planning to launch Intel 20A in the first half of the year and Intel 18A in the second half. However, it is speculated that Intel 20A will be exclusively used for Intel’s own products, maintaining a close collaboration with TSMC.

TSMC, adopting a cautious approach, benefits from a more advantageous cost structure by minimizing changes in production tools within the same process technology and manufacturing flow. For customers, altering designs during advanced process development incurs significant time and economic costs.

Supply chain sources reveal that TSMC finalized various parameters for its 2-nanometer process at the end of last year, confirming specialty gases and equipment. Contracts are gradually being signed, with equipment installation at the Baoshan P1 fab scheduled to commence in April. Equipment industry sources suggest that TSMC’s process advancement is progressing rapidly as expected, speculating that there will be updates on the Baoshan P2 fab later this year.

(Image: TSMC)