On February 16th 2026, MediaTek CEO Rick Tsai stated in his ISSCC 2026 keynote that the basic unit for measuring AI compute efficiency will no longer be just the AI chip, but the entire AI system, including interconnect architecture, power, and cooling. On May 4th 2026, GUC likewise announced a strategic technology partnership with Wiwynn to jointly develop rack/pod‑scale solutions, indicating that competition among AI chip design houses is expanding from the chip scale to the rack/pod scale.

This report therefore focuses on an in‑depth analysis of: (1) NVIDIA’s AI rack/pod‑scale strategy, (2) the rack/pod‑scale AI deployments of major CSPs, and (3) rack/pod‑scale solutions from ASIC design and service providers. The goal is to clarify each vendor’s current AI rack/pod‑scale layout and future trends, and to examine the competitive strategies of Taiwanese ASIC design and service providers.

Key Highlights

• AI efficiency metrics are shifting from standalone chips to full AI systems, including interconnect, power, and cooling.
• Industry competition is expanding from chip‑level to rack and pod‑scale system solutions. 
• The report analyzes NVIDIA’s rack/pod strategy and major CSP deployments.
• It assesses Taiwanese ASIC design and service providers’ system‑level strategies and future trends.

Table of Contents

1. NVIDIA’s Deployment in AI Rack/POD Scale
   • Figure 1: Seven Chips of NVIDIA’s Rubin Series
   • Figure 2: Five MGX Racks of NVIDIA’s Rubin Series
   • Figure 3: Schematics of Five MGX Rack Architectures for NVIDIA’s Rubin Series
   • Figure 4: Schematics of NVIDIA’s Vera Rubin POD
   • Table 1: NVIDIA’s Acqusition and Investment on AI Data Center Hardware between 2025 and May 2026
2. Deployment in AI Rack/POD Scale among Major CSPs
   • Figure 5: Comparison of AI Chip Architectures between NVIDIA and CSPs
   • Table 2: Performance Comparison of AI Chips between NVIDIA and Major CSPs
   • Figure 6: Comparison of AI Rack Architectures between NVIDIA and Major CSPs
   • Table 3: Comparison of AI Rack Architectures and Performance between NVIDIA and Major CSPs
3. Rack/POD Scale Solutions among ASIC Design and Service Providers
   • Figure 7: Broadcom’s Deployment in Rack Level
   • Figure 8: Broadcom’s Deployment in POD Level
   • Table 4: Reliable Data of Broadcom’s CPO Switches at Metas’ Data Centers
   • Figure 9: Marvell and Samtec Joined Hands to Work on CPC Solutions
   • Figure 10: Marvell’s Solutions at Rack/POD Level
   • Table 5: Comparison of MicroLED, VCSEL, and DFB as Laser Light Sources
   • Table 6: Overview of ASIC Designers’ AI Data Center-Related Product Lines
4. TRI’s View

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