As AI chips require increasingly stable power delivery, Si‑Cap (silicon capacitors) and their embedded/integrated packaging have become an important technological development direction, and key companies have successively announced silicon‑capacitor‑related plans, including SEMCO, which on April 14th 2026 announced plans to expand AI packaging production lines in Vietnam to produce Si‑Cap embedded substrates, and then in May revealed it had secured a long‑term contract of about US$1 billion from a major North American customer, and Analog Devices, which on May 19th 2026 announced a cash acquisition of the US Si‑Cap company Empower for US$1.5 billion in order to enter the AI supply chain.

This report mainly provides an in‑depth analysis of (1) the technical background of Si‑Cap, (2) the technological differences among major Si‑Cap vendors (Murata, SEMCO, AP Memory, Empower, TSMC, Samsung, Intel), and (3) the embedded/integrated Si‑Cap packaging requirements in the AI era, with the aim of explaining the technical principles of Si‑Cap, the reasons for growing demand, and the competitive landscape among existing vendors.

Key Highlights

• AI chip power delivery demands are driving Si-Cap (silicon capacitor) and embedded/integrated packaging as a key technology direction. 
• SEMCO expanding Vietnam AI packaging lines for Si-Cap embedded substrates, plus securing a major North American customer contract.
• Analog Devices acquiring US Si-Cap firm Empower to enter AI supply chain. 
• Report covers Si-Cap technical background, vendor comparison (Murata, SEMCO, AP Memory, Empower, TSMC, Samsung, Intel), and embedded packaging requirements in AI era.

Table of Contents

1. Technical Background of Si-Cap
   • Figure 1: Principle of Charging and Discharging for Capacitors
   • Figure 2: Schematics of Capacitor Structure and Formula of Capacitance
   • Table 1: Comparison of Materials and Features between Various Capacitors
   • Figure 3: Deep Trench Process of Si-Cap
   • Figure 4: Packable Positions of Si-Cap
   • Figure 5: Hierarchy of Capacitors
2. Analysis on Technology of Major Si-Cap Suppliers
   • Table 2: Comparison between Major Si-Cap Suppliers
   • Figure 6: IPDiA Embedded Si-Cap at Interposers
   • Figure 7: Packable Positions of SEMCO’s Si-Cap
   • Figure 8: Technology Roadmap of DRAM Processes
   • Figure 9: Packable Positions of AP Memory’s S-SiCap
   • Figure 10: Packable Positions of Empower’s ECAP
   • Table 3: Comparison of Embedded Si-Cap Technology among Foundries
   • Figure 11: TSMC’s eDTC in CoWoS Interposer
   • Figure 12: Samsung’s 2.xD Cube Platform
   • Figure 13: Intel’s eDTC/eMIM-T in EMIB Substrate
3. Demand for Embedded and Integrated Si-Cap Packaging in the AI Era
   • Table 4: Advanced Packaging Specifications for AI Chips, 2025-2028
4. TRI’s View

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