Summary

Under the influence of growing AI-related demand and the slowing pace of node migration under Moore’s Law, achieving lower power consumption and higher transistor counts on a single chip has become a major challenge. To address this, 3D stacking architecture has emerged as a key technology. TSMC anticipates that within the next several years, a single chip could contain as many as 200 billion transistors. Furthermore, TSMC aims to reach a milestone of over 1 trillion transistors through 3D packaging.

As the AI chip architectures for the integration of memory and logic ICs advance from 2.5D to 3D, breakthroughs in the development of hybrid bonding will be critical. This report examines the implications of these technological advancements, focusing on the growth in the demand for hybrid bonding and related processes as well as how this trend affects equipment providers.

Table of Contents
1. Introduction to Hybrid Bonding

2. Hybrid Bonding Process
  (1) Die Surface Preparation
  (2) Die-to-wafer Bonding  
  (3) Copper-to-copper Bonding through Annealing   

3. Additional CMP/Bonding and Dicing/Inspection and Testing Processes
  (1) Significant Growth in Demand for CMP
  (2) Wafer Sorting and Dicing  
  (3) Increase in Number of Measurement and Inspection Steps

4. Recent Activities of Key Equipment Providers
  (1) Applied Materials
  (2) Besi Semiconductor
  (3) ASM Pacific Technology 
  (4) EV Group (EVG)
  (5) Disco

5.TRI’s View
  (1) Hybrid Bonding Has Three Major Advantages; One of Them Is Significant Reduction in Chip
  Stack Thickness, Allowing for More Compact Designs
  (2) Rising Demand for CMP, Bonding, Dicing and Inspection/Testing Processes Will Drive
  Relevant Equipment Providers to Expand Their Operations and Product Offerings

＜Total Pages：12＞