According to ChinaTimes’s report, following Taiwan’s implementation of strict control on 22 core key technologies, several Taiwanese lawmakers are urging the country’s Ministry of Economic Affairs to also consider “mild control” for the export of mature semiconductor process equipment and industry talents from Taiwan to China. Furthermore, the Ministry of Economic Affairs emphasized its success in attracting semiconductor giants like AMD and NVIDIA.

Taiwan’s Minister of Economic Affairs, Wang Mei-hua, stated on the December11th that discussions across government departments would be necessary to include mature semiconductor processes and industry talents in the category of “mild export controls.”

The Ministry of Economic Affairs aims to present its view on this matter within three months. She emphasized the importance of ensuring Taiwan’s continued role in critical international supply chains.

Other officials under the ministry added that they are aware of China’s significant efforts to develop mature processes. They plan to conduct an analysis of the expansion of mature processes in China, and any regulatory responses will be based on the results of this analysis.

The officials noted that China aims for competitiveness in terms of price and quantity but emphasized that Taiwan has advantages in certain special semiconductor manufacturing processes. They expressed caution about Chinese IC design firms potentially impacting the lower-end market by placing orders with their compatriot foundries.

The Ministry of Economic Affairs highlighted its success in attracting major AI chip manufacturers, such as AMD and NVIDIA, to establish logistics and operational centers in Taiwan over the past two years.

NVIDIA has chosen to establish its hub warehouse logistics center within the Farglory  Free Trade Zone. NVIDIA’s product applications span both consumer and industrial sectors, with a future focus on investments in 5G, AI, autonomous vehicles, cloud computing, advanced applications, and data centers.

The establishment of a logistics center in Taiwan is expected to further increase the share of OSAT orders in Taiwan, driving development in Taiwan’s advanced IC packaging technology. Additionally, AMD initiated an assessment in 2022 for investing in a “mega” logistics center in Asia.

The Taiwanese Ministry of Economic Affairs held multiple meetings to facilitate communication between the company and the Ministry of Finance, explaining the project’s economic benefits to Taiwan. Finally, with successful coordination, AMD smoothly proceeded with the establishment of its logistics center in Taiwan.

AMD anticipates significant revenue growth from the logistics center, aligning with the demand for high-end AI server orders from the fourth quarter of this year to the next.

(Photo credit: NVIDIA)

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• [News] Taiwan Lists 22 Critical Technologies to Face Strict Controls, Included 14nm Processes and Beyond

On the 7th, TSMC convened the 2023 Supply Chain Management Forum, C.C. Wei, President of TSMC, acknowledging persistent inflationary pressures, remains optimistic about 2024. He also cited the rapid growth of AI applications as a key driver of opportunities, reported by CTEE.

Wei addressed the pivotal role of semiconductors in AI development. Looking ahead, the focus extends to continual AI technology advancement and computational power enhancement, with a parallel emphasis on energy consumption reduction. Given projections of AI computational demand tripling in the next 2 years, addressing energy efficiency becomes paramount.

To meet escalating AI computational needs, Wei highlighted the imperative to develop technologies balancing high performance with effective power control. TSMC commits to providing ample production capacity to meet end-user demands while sustaining cost-efficiency.

Global supply chain resilience amid challenges from society, economy, and geopolitics. Collaborating with partners. TSMC navigates 3nm, advanced and specialty processes for capacity expansions, R&D for 2nm and beyond, and global production plans. The company aims to lead through cutting-edge technology and top-notch manufacturing services, fostering innovation for customers.

Apart from the insightful speech, Wei also presented the 2023 Excellent Performance Award during the forum. It recognized suppliers’ performance in technology collaboration, global production support, green manufacturing, fab construction management, production capacity, quality control and other categories. Companies like Applied Materials, ASM International, KLA, Lam Research, TOKYO ELECTRON LIMITED and others.

(Image: TSMC)

In an announcement on December 5th, Taiwan’s National Science and Technology Council(NSTC) has designated 22 technologies, such as IC manufacturing and heterogeneous integration packaging, as national core key technologies. This inaugural list prioritizes technologies with leading advantages and immediate protection requirements.

NSTC, in collaboration with relevant ministries, plans to conduct a comprehensive review three months later, anticipating a second wave of additions or adjustments, as per reported by UDN News.

NSTC emphasized that the theft of classified national core key technologies through economic espionage will prompt legal investigations with enhanced penalties. Moreover, individuals receiving government subsidies exceeding half in national key technology businesses must obtain permission for travel to China.

Highlighting the significance of the semiconductor industry, especially considering Taiwan’s global market share and interconnected supply chain, the listed technologies include IC manufacturing for 14nm process and advanced processes beyond, encompassing critical gases, chemicals, and equipment. Heterogeneous integration packaging technologies, such as wafer and silicon photonics integration packaging, along with their essential materials and equipment, are also covered. Additionally, the list features chip security, post-quantum cryptography protection, and proactive network defense technologies, reflecting their relevance to information security.

NSTC highlighted the ongoing thoroughness of the list to safeguard industries. In this regard, it plans to collaborate with relevant ministries, keeping pace with technological advancements and the industrial development trajectories of nations like the United States and South Korea.

According to CNA’s report, the council will actively seek input from industry, government, academia, and research communities. A second wave of the list is expected to be presented after a comprehensive review three months later.

The highly anticipated 18th International Microsystems, Packaging, Assembly, and Circuits Technology Conference, also known as IMPACT 2023, took place with grandeur from October 25th to 27th at Hall 1 of Taipei Nangang Exhibition Center. This prestigious event was co-organized by leading institutions in the fields of electronics, including IEEE Electronics Packaging Society (IEEE EPS) – Taipei, International Microelectronics Assembly and Packaging Society (iMAPS) – Taiwan, Industrial Technology Research Institute (ITRI), and the Taiwan Printed Circuit Association (TPCA). Under the overarching theme of “IMPACT on the Future of HPC, AI, and Metaverse,” the conference delved deep into the realm of cutting-edge IC packaging and circuit board technologies that are specifically tailored for next-generation applications in HPC, AI, and the Metaverse.

At the opening ceremony, Dr. Wei-Chung Lo, the Chair of IMPACT 2023, President of iMAPS – Taiwan, and Deputy Director of the Electronic and Optoelectronic System Research Laboratories at the ITRI, noted that the event had attracted over 700 participants, with nearly 30% from overseas. This made IMPACT 2023 the largest industry event for advanced semiconductor packaging technologies in Asia. Dr. Lo expressed gratitude for the support from the IEEE EPS, iMAPS, International Electronics Manufacturing Initiative (iNEMI), and Japanese associates including the International Conference on Electronic Packaging (ICEP) and Japan Institute of Electronics Packaging (JIEP). He also thanked the tremendous support from individuals and organizations across the industry and academia.

Innovations in Critical 3D Packaging Technologies and System-Level Performance Upgrade Will Trigger a Surge of New AI Applications

Following the opening ceremony, plenary speeches were delivered by Dr. Jun He, Vice President of Quality and Reliability and Operations and Advanced Packaging Technology and Service at TSMC, and Dr. Raja Swaminathan, Corporate Vice President at AMD. During his speech, Dr. He emphasized the explosive growth in the 3D packaging technology market, with a projected global market value exceeding USD 100 billion by 2025. Dr. He also highlighted TSMC’s proactive approach in aggressively promoting its “3DFabric” platform, which combines advanced packaging technologies such as SoIC (3D), CoWoS (2.5D), and InFO (2.5D). As a testament to the power of 3D packaging technology, he pointed out that NVIDIA’s latest generation GPU (i.e., the H100) has achieved a remarkable six-fold performance improvement compared to its predecessor (i.e., the A100).

The strong demand for HPC is fueling the extensive commercial adoption of 3D packaging technology. In light of this trend, TSMC plans to expand its cleanroom space for the 3D packaging process, with expectations of more than doubling it by 2025. Furthermore, TSMC is expediting collaborations with ecosystem partners to advance critical 3D packaging innovations. One example is hybrid bonding, which enhances interconnect density. Another example is key innovations in 3D packaging that optimize signal integrity for HBM.

▲Dr. Jun He, Vice President at TSMC, highlights the game-changing impact of 3D packaging technology on NVIDIA’s latest GPU, showcasing a remarkable six-fold performance improvement over its predecessor. The surge in demand for HPC is propelling the extensive adoption of 3D packaging technology across commercial applications. Anticipating this trend, TSMC is set to significantly expand its cleanroom space for 3D packaging, with plans to more than double it by 2025. (Source: IMPACT)

Dr. Swaminathan, Corporate Vice President of AMD, said that the demand for supercomputers and AI performance had previously been growing exponentially, doubling every 1.2 years. However, the growth rate has become even higher recently, doubling within a year. The industry’s primary focus lies in upgrading system-level performance through innovations in high-speed interfaces, advanced packaging, and heterogeneous integration. AMD, in particular, is directing its attention toward improving inter-chip communication and energy efficiency. Leveraging its evolving 3D stacking technology and hybrid bonding packaging, AMD aims to substantially reduce power consumption in inter-chip communication. AMD anticipates that it will achieve a 30-fold increase in HPC and AI training efficiency per watt over the next five years.

In summary, TSMC and AMD, as respective leaders in foundry services and IC design, are focusing on the synergistic relationship between advanced packaging technologies and next-generation AI architectures. They recognize that these two sets of technologies work together to drive substantial improvements in the computing capabilities of semiconductor chips.

▲AMD’s Corporate Vice President, Dr. Raja Swaminathan, stated that the 3D stacking and hybrid bonding technologies being developed by his company can significantly reduce the power consumption of inter-chip communication. AMD also forecasts a 30-fold increase in HPC and AI training efficiency per watt in the next five years. (Source: IMPACT)

Collaborative Design to Spark Major Transformations in AI, and High-Density Heterogeneous Integration Platform to Become Crucial Bridge to Future of Semiconductor Technology

This year’s conference marked the third edition of the IEEE EPS Panel Discussion / Forum, presided over by Dr. C. P. Hung, Vice President of the ASE Group. As a key organizer of the IMPACT conference, the IEEE EPS once again brought together the latest R&D findings and influential speakers to facilitate the exchange of information regarding the most recent trends and technological advancements within the semiconductor and electronics industries.

The inception of the IEEE EPS Panel Discussion has seen a progression of significant themes. The first edition centered on the realm of 5G, followed by the second edition that explored edge computing. Notably, this year’s panel was jointly organized with the IEEE Council on Electronic Design Automation (CEDA). The primary focus of this year’s panel discussion – also known as the IEEE EPS and CEDA Joint Panel – was on ECAD tools capable of optimizing the collaborative design process for chips, packages, and systems.

The idea to join forces with the IEEE CEDA originated from Dr. Bill Chen, Fellow and Senior Technical Advisor at the ASE Group. Delivering his remarks remotely from a different location, Dr. Chen emphasized that although AI and machine learning are still in their nascent stages, significant transformations are anticipated over the next few decades. Dr. Chen stressed that collaborative design will drive the development of AI-related products and applications. This trajectory of development will also necessitate the establishment of an open-source chip ecosystem and standardized interfaces to continuously improve efficiency.

▲Dr. C. P. Hung, Vice President of ASE Group and moderator of the IEEE EPS Panel Discussion, stated that this year’s theme, which was jointly developed with the IEEE CEDA, focuses on ECAD tools that optimize collaborative design across chips, packages, and systems. (Source: IMPACT)

In addition, the IEEE EPS and CEDA Joint Panel specially invited renowned scholars and experts from domestic and international backgrounds. Prominent speakers include Dr. Madhavan Swaminathan, Head of the Department of Electrical Engineering at Pennsylvania State University; Dr. Chih-ming Hung, MediaTek’s Assistant Vice President of Technology; Dr. Arvind Sundarranjan, Managing Director at the Applied Packaging Development Center (APDC); Dr. Kyu Lim Sung, Professor at the Georgia Institute of Technology; Dr. Debendra Das Sharma, Intel’s Senior Fellow; and Nan Wang, Vice President of Component Quality and Technology at Cisco.

Dr. Madhavan Swaminathan stressed that high-density heterogeneous integration platforms will be a future trend. Moreover, such platforms have to incorporate a wide range of technologies from antennas to AI to support applications related to network communication and edge computing. This means that R&D and collaborative design also have to take place simultaneously across various fields, with distributed computing and telecommunication solutions playing crucial roles. On the topic of AI-assisted design, Dr. Hung from MediaTek discussed the importance of synergy among material technology, mechanical engineering, EDA tools, etc. However, Dr. Hung also noted that not all advances in these fields have immediate practical uses in the development of AI applications. In the case of 3D AI machine learning, the maturity of the tools for training needs to be considered.

Turning to the topic of hybrid bonding, Dr. Madhavan Swaminathan pointed out that it is a key technology in advancing AI and HPC, as it brings about computing solutions that can handle massive amounts of data with reduced latency and greater power efficiency. On the other hand, hybrid bonding is a highly complex manufacturing process that involves at least hundreds of steps. Optimizing individual steps one at a time is not enough; synergistic progress has to take place across numerous sections of the process in order to raise the yield rate.

Dr. Sung believes that initiating the next wave of the “AI revolution” will require collaborations among various types of chips, and EDA tools provide the necessary support for the development of 2.5D and 3D packages. Besides being the indispensable assistant for chip designers, EDA tools can also contribute to decision-making regarding materials and bonding methods.

As for how the UCIe standard can contribute to the expansion of the ecosystem for small-sized chips, Dr. Debendra Das Sharma said that UCIe allows for the mixing and matching of multiple chips at the package level to overcome manufacturing limitations and increase yield rates. Currently supporting 2D and 2.5D packages, UCIe will also be introduced to 3D packages in the future. When building SoCs, this standard enables innovations at the package level, integrating not only CPU, GPU, and memory but also supporting interfaces such as USB, PCIe, and CXL. The adoption of UCIe is expected to result in dynamic and configurable systems.

Likewise, when discussing the topic of heterogeneous integration, Cisco’s Vice President Wang, mentioned Open Platform Communications (OPC), a set of standards and specifications for industrial telecommunication. Wang said that co-packaged optics, which falls under OPC, can effectively address the challenges related to power consumption and costs associated with the increasing demand from machine learning networks for high-speed connectivity and high-volume computing capability. With OPC technologies, optical components can be closely integrated with Ethernet switch ICs and packaged on the same substrate, thereby reducing system power consumption by as much as 30%. However, the adoption of OPC will bring new challenges related to the integrity of signals and power supply. Hence, collaborative design and system-level optimization are necessary to achieve large-scale application.

▲The IEEE EPS and CEDA Joint Panel featured a strong lineup of speakers. From left to right: Yao-wen Chang, Dean of the College of Electrical Engineering and Computer Science at National Taiwan University; Dr. Arvind Sundarranjan, Managing Director at the APDC; Dr. Chih-ming Hung, MediaTek’s Assistant Vice President of Technology; Dr. Madhavan Swaminathan, Head of the Department of Electrical Engineering at Pennsylvania State University; Dr. C. P. Hung, Vice President of ASE Group; Nan Wang, Vice President of Cisco; Dr. Kyu Lim Sung, Professor at the Georgia Institute of Technology; and Dr. Debendra Das Sharma, Senior Fellow at Intel. (Source: IMPACT)

Seeking the Best Collaborative Design Tools to Rapidly Address the Needs in the Market for Heterogeneous Integration Solutions

In the second half of the joint panel, Dr. Yao-wen Chang, Dean of the College of Electrical Engineering and Computer Science at National Taiwan University, took over as the moderator. He raised three questions for the experts to discuss and share their insights. The first question he posed was, “How can AI and advanced packaging technologies address the most challenging issues in the development of applications related to AI and edge computing?” Dr. Swaminathan from Penn State was the first to respond, explaining that AI requires large-scale computing and thus requires cooperation among chips made with different process nodes. This also means that advanced packaging technologies can facilitate the integration of various types of chips, including RF chips, GPUs, CPUs, and even optical components.

Dr. Hung from MediaTek cited successful cases of AI being applied to power supply analysis and chip layout optimization. However, the bottleneck in advancing 3D integration lies in the lack of data, so AI cannot fully replace humans in designing chips at the present moment. Dr. Sung also pointed to insufficient data related to circuit designs. This impose limitations in supervised learning. Currently, the academic community is ramping up research efforts in unsupervised learning and reinforcement learning. Cisco’s Vice President Wang said heterogeneous integration could address certain challenges in the development of network systems, but he also acknowledged that chip design and chip manufacturing could become more complex as a result.

▲IMPACT 2023 was a major gathering of elites in the semiconductor and electronics industries. The event attracted a huge number of professionals from various sectors to come to the venue and exchange market intelligence and ideas. (Source: IMPACT)

The second question was, “What are the key technological challenges that we must overcome when the next generation of AI interacts with human intelligence? And when can we expect to see solutions to these challenges?” In response to this question, Dr. Das Sharma said that heterogeneous integration can combine processors and memory in a single package, while 3D stacking can further narrow the distance of inter-chip communication, thereby leading to a faster data transfer rate, better performance, and less power consumption. Dr. Sundarrajan also pointed out that solving the challenges of heterogeneous integration will necessitate technological innovations in materials and other areas. Reducing the space between the chip and the substrate, lowering the defect rate, finding ways to strengthen the bond between different materials, and eliminating chip warping are some of the issues mentioned in the joint panel. These kinds of solutions are required to enable chips to achieve the most optimal performance.

The final question posed by Dr. Chang was, “Regarding EDA tools, what is the extent of their readiness for advanced packaging? And what are the major technological gaps that require immediate attention?” In answering this question, Dr. Sung said that the development of EDA tools is somewhat lagging behind when it comes to heterogeneous integration and the construction of 2.5D and 3D packages. Overall, chip designers need more functionality and automation from their EDA tools. While tools for 2D packages are quite mature, there is still considerable room for improvement in designing chips featuring 3D integration. Dr. Madhavan Swaminathan added that current providers of EDA tools tend to be too passive. They are reluctant to invest in new technologies without specific orders from customers. Swaminathan believes EDA companies need to partner with other technology developers to push forward heterogeneous integration.

Dr. Hung stated that even for 2D packages, chip design companies need to have their own in-house tools to address the shortcomings of commercial EDA tools from external providers. Dr. Hung believes EDA companies should respond more promptly to the needs of IC design houses. Turning to Dr. Das Sharma, he stated that when EDA companies see market potential, they will invest in new technologies. The key is to make them recognize that the aforementioned technologies represent the next major direction in the evolution of chip designs. Lastly, Cisco’s Wang called attention to the different integration and analytical capabilities that EDA tools and systems have to have in order to prepare for the potential issues that may arise in the future development of heterogeneous integration. Early preparations are essential.

▲The IEEE EPS and CEDA Joint Panel primarily delved into discussions on the following topics: (1) the use of AI and advance packaging technologies for resolving issues in the development of edge computing and AI-driven applications; (2) the major technological challenges in the development of next-generation AI; and (3) the use of EDA tools to further improve the designs of advanced packages. (Source: IMPACT)

As a collaborative effort between its organizers and a consortium of partnering entities, IMPACT 2023 unfolded as a massive three-day convention, featuring 33 sessions comprising seminars, panel discussions, lectures, and more. The event not only included keynote presentations by top executives from companies like TSMC and AMD but also assembled hundreds of heavyweight experts from academia and accomplished professionals from various industries worldwide. Additionally, the IEEE EPS and CEDAS Joint Panel was held for the first time, offering attendees an in-depth look into the realm of AI-based collaborative design. Embracing a holistic approach, IMPACT 2023 transcended mere technological discourse to explore the contours of market trends, igniting the sparks of innovation that promise to shape our future.

It is worth noting that TPCA Show 2023 was held concurrently, featuring 1,386 booths set up by companies around the world. More than 480 international brands were showcasing their products and services at this event. In terms of thematic focus, the exhibitions at TPCA Show 2023 were primarily about semiconductors (i.e., chip assembly and packaging), net-zero emissions, smart manufacturing, and forward-looking solutions. The organizers of TPCA Show 2023 were eager to provide a wide range of services to foreign visitors as they sought to make the event the premier international platform for presenting the latest innovations and trading cutting-edge solutions. Like IMPACT, TPCA Show aims to promote the development of various industries. These events also continue to demonstrate Taiwan’s capabilities in the areas of PCBs, semiconductors, electronics, etc.

(The featured image of this article shows Dr. Wei-chung Lo delivering the opening remarks on the first day of IMPACT 2023. Dr. Lo is the Chair of IMPACT 2023, President of iMAPS – Taiwan, and Deputy Director of the Electronic and Optoelectronic System Research Laboratories at ITRI. Source: IMPACT.)

According to South Korean media The Elec’s report, due to strong demand from Chinese chip manufacturers and wafer foundries, the shortage of photomasks in the market has not eased, and it is anticipated that prices will rise in 2024.

The report notes that most photomask manufacturers, including Japan’s Toppan, DaiNippon Printing, and the U.S.’s Photronics, are currently operating at full capacity with a utilization rate of 100%. Some Chinese chip companies are even willing to pay additional fees to expedite delivery schedules.

In the field of integrated circuits, the function of a photomask is similar to the “film” in a traditional camera. With the collaboration of exposure and development processes in photolithography machines and photoresist, the pre-designed patterns on the photomask are transferred to the photoresist on the substrate, enabling mass production through image replication.

Photomasks play an indispensable role in the semiconductor chip manufacturing process, especially in advanced processes where more intricate circuit patterns require multiple layers of photomasks to aid production. For example, mature processes may require around 30 photomasks, while the latest advanced processes might demand as many as 70 to 80 photomasks to handle.

Currently, Chinese foundry giant SMIC employs Deep Ultraviolet (DUV) technology to produce 7nm chips. Compared to Extreme Ultraviolet (EUV), DUV requires more photomasks for the fabrication of multiple circuit patterns.

Toppan Printing, in its latest quarterly financial report covering July to September, anticipates a continual increase in demand for photomasks throughout 2023. DaiNippon Printing expressed agreement with this assessment in its half-year financial report for the period from April to September.

The graphic dimensions, precision, and manufacturing technology requirements of semiconductor photomasks continue to increase, with only a 3% domestication rate for high-end photomask versions in China. In the preparation of photomasks, the Chinese semiconductor photomask industry faces a situation where high-end equipment and materials are dominated by foreign manufacturers.

In the photomask industry chain, the upstream sector primarily involves equipment, substrates, light-blocking films, and chemical reagents; the midstream sector is photomask manufacturing, and the downstream sector includes chips, flat panel displays, touchscreens, circuit boards, and more.

The urgent demand for domestic substitutes for photomask versions is apparent, and the revenue scale of Chinese photomask manufacturers still has a considerable gap compared to leading overseas manufacturers.

(Photo credit: Toppan)