[News] TSMC’s Latest Advancements in CFET, 3D Stacking, and Silicon Photonics

Kevin Zhang, Senior Vice President of Business Development at TSMC, introduced the company’s latest technologies at the International Solid-State Circuits Conference (ISSCC) 2024. According to TechNews citing from the speech, Zhang shared insights into future technological advancements, prospects for advanced processes, and the latest semiconductor technologies needed in various fields.

Zhang noted that since the introduction of ChatGPT and Wi-Fi 7, a lot of advanced semiconductor are required, as we are entering an accelerated growth period for semiconductor going forward.

In the automotive sector, the industry is undergoing a revolution, with many suggesting that new vehicles will be software-defined. However, Zhang believes it’s more about silicon-defined because software needs to run on silicon, driving the future of autonomous driving capabilities.

CFET (Complementary Field-Effect Transistor)

In terms of technology, Transistor remain at the heart of the innovation, silicon innovation. It has shifted from geometry reduction to architectural innovation and the use of new materials. Moving from 16-nanometer FinFET to today’s 2-nanometer Nano Sheet technology represents significant progress in high-performance computing and architectural innovation.

What’s next? The answer is CFET.

Kevin Zhang explained that CFET involves stacking nMOS and pMOS on top of each other, significantly improving component currents and increasing transistor density by 1.5 to 2 times.

Alternatively, efforts are being made to create higher-performance switching devices from low-dimensional materials such as 2D materials, surpassing today’s devices or transistors.

Kevin Zhang also showcased that TSMC has successfully fabricated CFET architectures in the laboratory, stating, “This is a real integrated device that has been fabricated in our lab. Here, you see the transistor IV curve. They are beautiful curves. So, this is a significant milestone in terms of continuing to drive the innovation of the transistor architecture.”

However, as the geometry of the transistor shrinks, it becomes increasingly difficult and costly. This necessitates collaboration between process development teams and design research to achieve optimal benefits, known as “Design-Technology Co-Optimization” (DTCO).

In addition, TSMC has introduced FINFLEX technology, enabling chip designers to choose and mix the best fin structures to support each critical functional block, achieving optimal performance, density, and power consumption.

Another example of DTCO is Static Random Access Memory (SRAM). SRAM has scaled from 130 nanometers to the current 3 nanometers, and TSMC has achieved a over 100x density improvement, a result of collaboration or combination of a process innovation and adoption of the more advanced design technique.

Nevertheless, the essence or the objective of this technology scaling is for “energy efficient compute,” as Kevin Zhang expressed. He stated that in the entire semiconductor industry, TSMC has come a long way, and this progress has made today’s AI possible.

  • Advancements in HPC/AI Technology Platforms: 3D Stacking, Silicon Photonics, CPO

Whether it’s GPUs, TPUs, or customized ASICs, they all feature this particular integration scheme. Currently, the mainstream is 2.5D packaging. However, to meet future high-performance computing demands, this platform needs significant enhancement, requiring higher density and lower power consumption computation.

Therefore, stacking is needed, including integrating many memory bandwidths and HBM into the package, while considering issues such as power supply, I/O, and interconnect density.

Consequently, Kevin Zhang stated that bringing “silicon photonics into packaging” is the future direction. However, this will face many challenges, such as Co-Packaged Optics (CPO) closer to the electronic side.

1. 3D Stacking

When it comes to 3D stacking, Kevin Zhang presented a diagram and explained that to achieve higher interconnect density, specifically Chip-to-Chip connections, 3D stacking allows the bonding pitch to scale to just a few micrometers, achieving interconnect density like monolithic. “That’s why the 3D (stacking) is the future,” he concluded.

2. Silicon Photonics / Co-Packaged Optics (CPO)

Kevin Zhang pointed out that while electronics excel at computation, photons are better for signaling or communication. He illustrated that if a 50 terabyte switch, an all-electronic copper system were used, it would consume 2,400 W.

The current solution involves using pluggable modules, which can save 40% of power (> 1500W). However, as the need for higher-speed signals and larger bandwidths increases in the future, this solution falls short. Therefore, integrating silicon photonics technology is necessary to introduce photon capabilities.

  • Automotive Technology
  1. Pursuing Low DPPM

Fundamentally, the latest automotive technologies require significant computational power, but power consumption is becoming a concern, especially for battery-powered vehicles.

Kevin Zhang states that automotive semiconductor technology has lagged behind consumer or HPC technologies by several generations due to stringent safety requirements. The DPPM (Defects Per Million) for automotive applications must be close to zero.

Therefore, fabs, semiconductor manufacturers, and automotive designers must collaborate more closely to accelerate this pace. He also promises, “you will see 3 nanometer in your car before long.”


As automotive transitions to a domain architecture, MCUs (Microcontroller Units) become increasingly important and require advanced semiconductor technology to provide computational capabilities.

Traditional MCUs mostly rely on floating-gate technology, but this technology encounters bottlenecks below 28 nanometers. Fortunately, the industry has invested in new memory technologies, including new non-volatile memories such as Magnetic Random Access Memory (MRAM) or Resistive Random Access Memory (RRAM).

Therefore, transitioning from MCU to MRAM or RRAM-based technologies helps drive continuous technology scaling from 28 nanometers to 16 nanometers, or even 7 nanometers.

  • Sensor and Display: CIS (CMOS Image Sensors)

Sensor technology has evolved from simple 2D designs and single layer design to intelligent systems with 3D wafer stacking, essentially layering the signal processing on top of the sensing layer.

Kevin Zhang also mentioned, “our technologies already start investing, researching on the multi-layer design.”

Engaging in three or more layer designs allows for the optimization of pixels, continuing the trend of scaling pixel sizes while meeting resolution requirements and achieving optimal sensing capabilities simultaneously.

Another example is AR (Augmented Reality) and VR (Virtual Reality), where separating memory layers and stacking them onto other logic chips can effectively reduce size while maintaining high-performance demands.

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(Photo credit: TSMC)

Please note that this article cites information from TechNews and ISSCC.

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