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At CES 2026, NVIDIA takes the lead with its next-generation Rubin, positioning itself as the initial, exclusive HBM4 client currently. While the AI chip giant is certainly reshaping the HBM4 landscape, TrendForce observes it has pushed per-pin speeds above 11 Gbps, forcing SK hynix, Samsung, and Micron to revise HBM4 designs. With all three resubmitting samples and strong demand from Blackwell, HBM4 mass production is now expected no earlier than the end of 1Q 2026, as noted by TrendForce.
Thus, now is a prime moment to take stock of the memory giants and their HBM4 strengths. Here’s a quick roundup of their latest developments and the challenges that lie ahead.
SK hynix Accelerates 16-Layer HBM4 Ahead of 12-Layer Ramp-Up
As the current HBM leader, SK hynix is pushing the frontier by showcasing its 16-layer HBM4 at CES, making it the first company to do so. According to Etnews, the new 16-layer, 48 GB HBM4 builds on the 12-layer, 36 GB model, which already set a speed record of 11.7 Gbps. By stacking DRAM up to 16 layers, SK hynix significantly boosts both capacity and speed, achieving bandwidth exceeding 2 TB per second.
However, The Korea Herald highlights that scaling from 12 to 16 layers is far tougher than the jump from 8 to 12. Analysts cited by the report estimate that 16-layer HBM requires wafers to be thinned to around 30 µm, compared with roughly 50 µm for current 12-layer designs. With JEDEC limiting HBM4 package height to 775 µm, conventional methods leave little room for further scaling, highlighting the technical hurdles ahead, the report notes.
While the industry increasingly sees hybrid bonding as the long-term answer to the challenge, SK hynix is taking the lead today by stabilizing yields with its MR-MUF (Mass Reflow Molded Underfill) process. Samsung and Micron, meanwhile, continue to rely on the TC-NCF (Thermal Compression with Non-Conductive Film) approach.
According to SK hynix, MR-MUF heats and interconnects all the vertically stacked chips in HBM products at once, which makes it more efficient than TC-NCF which applies a film-type material after each chip is stacked.
As SK hynix highlights, because the DRAM chips in 12-layer HBM3 had to be about 40% thinner than those used in 8-layer HBM3 to keep the overall package height in check, chip warpage emerged as a major issue. To address this, the memory giant introduced a new EMC material under its Advanced MR-MUF process, improving heat dissipation by about 1.6× compared with the original version.
TechNews observes that while the company is also developing hybrid bonding as a fallback, its core strategy is to extend the life of its industry-leading MR-MUF technology for as long as possible.

(Credit: SK hynix)
Samsung’s 1c DRAM Gives HBM4 a Head Start; Hybrid Bonding in Play
On the other hand, TrendForce notes that compared with its peers, Samsung has taken an early lead by adopting a 1c nm process (10nm-class, 6th-generation) for HBM4 and utilizing advanced in-house foundry technology for the base die. This approach, as per TrendForce, is expected to enable higher transmission speeds, positioning Samsung as the most likely supplier to qualify first and potentially gain an advantage in supplying higher-end Rubin products.
According to Chosun Biz, Samsung has applied a 4nm logic process on its 1c DRAM-based HBM4 and fine-tuned the design to deliver speeds exceeding 11Gbps, surpassing customer requirements. Etnews previously reported that as rivals built HBM4 on the older 1b DRAM node, Samsung aimed to change the game by moving to the more advanced 1c process. The company has now started production of its 1c DRAM, with yields reportedly nearing its 80% mass-production target, the report added.
Notably, Sisa Journal suggests that while SK hynix sticks to the traditional MR-MUF method for 16-layer HBM, Samsung is reportedly racing ahead with hybrid bonding, aiming for 16-layer HBM4E products by 2028. However, the report adds while Samsung is already supplying hybrid-bonded HBM4 prototypes to key customers, including NVIDIA, yields remain low at around 10%.
As the memory giant with the most evenly distributed capacity, Samsung isn’t just relying on technology to make its mark in the HBM4 era. Riding strong demand, Etnews reports that the company plans to boost HBM production by 50% in 2026, reaching around 250,000 wafers per month by year-end, with the expansion focused squarely on HBM4.
Micron Speeds up Capacity Expansion
Micron, which fabricates its HBM4 on the 1‑beta node, said in its December earnings call that the product achieves industry-leading speeds above 11 Gbps and is on track for high-yield ramp-up in the second quarter of 2026. The company highlighted that both the base logic and DRAM core dies are designed and manufactured in-house using advanced CMOS and metallization process technologies.
Though details on Micron’s HBM4 are still relatively limited, Etnews reports the company is leveraging its low-power HBM expertise to challenge Korean rivals by locking in more production capacity. It’s rapidly advancing from 12-layer HBM4 toward 16-layer products while steadily growing its market presence, the report adds.
New Daily, citing CEO Sanjay Mehrotra’s remarks, points out that Micron’s upcoming Singapore advanced packaging plant and Hiroshima facility in Japan are expected to substantially ease production capacity constraints, the report adds.
The race for HBM4 is heating up at unprecedented speed. While 12-layer HBM4 has yet to fully ramp, NVIDIA’s request for 16-layer supply in the second half of 2026 has put memory giants on high alert, Etnews reports.
For now, SK hynix is leading with its refined MR-MUF process and early 16-layer demos, Samsung is pushing 1c DRAM and hybrid bonding to leap ahead, and Micron is expanding capacity to close up the gap. The first company to overcome the technological hurdles of 16-layer stacking will not only meet the surging AI demand but is poised to seize the next-generation market crown, setting the stage for a fierce showdown in the HBM4 era.
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(Photo credit: SK hynix)