[News] TSMC Says CoWoS Offers Industry’s Largest Reticle-Size Packaging Amid Intel EMIB Rivalry; CoPoS Advances
TSMC holds its earnings call today, with its response closely watched amid rising industry interest in rival Intel’s advanced packaging technologies, including EMIB. In response, according to TechNews, TSMC Chairman and CEO C.C. Wei states that the company continues to offer the industry’s largest reticle-size packaging solutions and, together with SoIC (System-on-Integrated-Chips), is confident in providing customers with the best options.
On its current packaging strategy, TSMC states that its primary advanced packaging approach is CoWoS. According to TechNews, citing institutional investors, TSMC’s CoWoS capacity is expected to reach around 115,000 to 140,000 wafers per month by the end of 2026, and further increase to approximately 170,000 wafers per month in 2027. The report adds that expansion will be mainly concentrated in Tainan and Chiayi, with a scale significantly exceeding previous levels.
Looking beyond CoWoS, Wei states that the company is actively advancing CoPoS (Chip-on-Panel-on-Substrate) panel-level packaging. As TechNews highlights, supply chain sources indicate that TSMC’s CoPoS pilot line completed major equipment installation in February this year, with full line setup expected by June. The market expects mass production to begin as early as 2028 to 2029, with broader adoption anticipated in the following years.
In terms of technology advantages, TechNews notes that by adopting panel-level processes, CoPoS helps overcome traditional packaging size limitations, improve output efficiency per unit area, and lower overall packaging costs, making it particularly attractive for large-chip applications such as AI ASICs and GPUs.
Read more
- [News] TSMC on Terafab: No Shortcuts in Foundry; Reportedly Confirms Next-Gen NVIDIA LPU Project amid Samsung Rivalry
- [News] NVIDIA Rubin Ultra and Feynman Reportedly to Boost TSMC SoIC; Besi, Applied Materials, TEL to Benefit
(Photo credit: TSMC)
