[News] TSMC’s 2nm Fab in Kaohsiung Prepares for N2P Mass Production

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In the ongoing global race for advanced semiconductor technology, TSMC, the leader in semiconductor manufacturing services, continues its strides towards 2nm project. The Hsinchu’s Baoshan plant is set to commence equipment installation in Q2 2024, with mass production scheduled for Q4 2025, starting with a monthly output of around 30,000 wafers. Meanwhile, TSMC fab in Kaohsiung is organizing for N2P mass production, featuring backside power supply tech, a year after N2’s debut.

According to a report by Taiwan’s Money DJ, as previously shared by TSMC, the N2 process introduces a backside power rail solution, ideal for high-performance computing (HPC) applications. The backside power rail promises a 10% to 12% speed boost and a 10% to 15% logic density improvement. The aim is to introduce backside power rail to customers in H2 2025, aligning with supply chain reports.

Notably, Intel led the transition from planar transistors to FinFET, and now, with evolving technologies like MBCFET, BSPDN (Backside Power Delivery Network) based on Gate-All-Around (GAA) FET. Major players such as TSMC, Samsung, and Intel actively compete for leadership in the next-gen GAA technology, and have further presented promising and proactive technology roadmaps.

According to Samsung Semiconductor’s plans, they target to implement the 2nm process into mass production by 2025, with 1.4nm scheduled for 2027. Intel, adopting RibbonFET transistor architecture based on GAA technology, anticipates pilot production of the 20A version in H1 2024 and mass production of the 18A in 2025.