A Glimpse into the Adoption Challenges and Technological Planning of TSMC’s 3nm Technology from the TSMC Techonology Synposium

Last Modified

2024-05-10

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Summary
TSMC president C.C. Wei was questioned by analysts about the potential introduction of High-NA EUV during TSMC’s 4Q23 earnings call. He responded, “Because of technology itself is no value. Only when that can serve your customer. So we always work with our customers to give them the best transistor technology and the best power-efficient technology and at a reasonable cost, okay? And more importantly, the technology maturity that—in the high-volume production, that's all important. Everything. Everything counted together. So we—every time we know that there are some new structure, new tools such a high-NA EUV, we look at it carefully, look at the maturity of the tools, look at the cost of the tools and look at the schedule of that—how to achieve it. We always make the right decision at the right moment to serve our customers.”

Table of Contents
1. The Insurmountable Challenge of 3nm Technology

2. Many TSMC Customer Halt Progress Before 3nm

3. Advanced Packaging Reveals Cutting-Edge Insights

4. Silicon Photonics: Not NVIDIA’s Preferred Chip Interconnect Solution?

5. TRI’s View

＜Total Pages：19＞

Sector: Wafer Fabrication / Foundry Semiconductors

Tag: AI Chip Silicon Photonics Advanced Packaging 3nm Competitive Landscape Production Capacity Technology Roadmap TSMC NVIDIA

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