InFO


2024-10-04

[News] TSMC Announces Partnership Expansion with Amkor to Collaborate on Advanced Packaging in Arizona

Amkor and TSMC announced today that the two companies have signed a memorandum of understanding to collaborate and bring advanced packaging and test capabilities to Arizona, further expanding the region’s semiconductor ecosystem.

Amkor and TSMC have been closely collaborating to deliver high volume, leading-edge technologies for advanced packaging and testing of semiconductors to support critical markets such as high-performance computing and communications. Under the agreement, TSMC will contract turnkey advanced packaging and test services from Amkor in their planned facility in Peoria, Arizona. TSMC will leverage these services to support its customers, particularly those using TSMC’s advanced wafer fabrication facilities in Phoenix. The close collaboration and proximity of TSMC’s front-end fab and Amkor’s back-end facility will accelerate overall product cycle times.

The companies will jointly define the specific packaging technologies, such as TSMC’s Integrated Fan-Out (InFO) and Chip on Wafer on Substrate (CoWoS) that will be employed to address common customers’ needs.

The agreement underscores the shared commitment to supporting customer requirements for geographic flexibility in front-end and back-end manufacturing, as well as fostering the development of a vibrant and comprehensive semiconductor manufacturing ecosystem in the United States. The companies’ shared vision is to enable seamless technology alignment for customers across a global manufacturing network.

“Amkor is proud to collaborate with TSMC to provide seamless integration of silicon manufacturing and packaging processes through an efficient turnkey advanced packaging and test business model in the United States,” said Giel Rutten, Amkor’s president and chief executive officer.

“Our customers are increasingly depending on advanced packaging technologies for their breakthroughs in advanced mobile applications, artificial intelligence and high-performance computing, and TSMC is pleased to work side by side with a trusted longtime strategic partner in Amkor to support them with a more diverse manufacturing footprint,” said Dr. Kevin Zhang, TSMC’s Senior Vice President of Business Development and Global Sales, and Deputy Co-COO.“We look forward to close collaboration with Amkor at their Peoria facility to maximize the value of our fabs in Phoenix and provide more comprehensive services to our customers in the
United States.”

(Photo credit: Amkor)

Please note that this article cites information from Amkor.

2024-08-15

[News] Google’s Tensor G5 Reportedly Manufactured with TSMC’s 3nm and InFO-POP Packaging

Google has accelerate its pace on the Pixel series, as the tech giant launched Google Pixel 9 on August 13th, which is two months ahead of its schedule.

Though the Tensor G4 processor in the model is manufactured with Samsung’s 4nm, according to a report citing sources by Commercial Times, Google is said to be switching to TSMC’s 3nm process with its next-generation Tensor G5, coupling with the foundry giant’s InFO-POP packaging.

Google’s Pixel 8 is said to be the first AI-centric smartphone, featuring a range of AI functionalities. Yet, Commercial Times’ report has indicated that, after years of close collaboration, Google will part ways with Samsung and have TSMC produce the Tensor G5 chip.

The chip is also said to adopt TSMC’s advanced InFO-POP packaging. Google’s move, according to the report, demonstrates its ambition to expand its leadership in software to hardware, as it eyes for the opportunities of edge AI.

Industry sources cited by the report further point out that in the fourth quarter, both Qualcomm and MediaTek will launch flagship-level chips, while Apple’s A18 will also be produced using TSMC’s N3 process.

All these developments have hinted at tech giants’ ambition on the massive potential of the edge AI market. Now, Google would be the latest competitor to join the race.

Meanwhile, though Pixel’s market share is relatively low, the Android ecosystem, with its 70% market share in smartphones and billions of users, offers significant potential. Google is said to be following a path similar to Apple’s, achieving complete integration of hardware and software to maximize this potential.

Google’s self-developed chip extends beyond mobile devices, with its TPU (Tensor Processing Unit) now in their seventh generation. Additionally, Google’s Arm-based CPUs are being developed in partnership with TSMC.

Read more

(Photo credit: Google)

Please note that this article cites information from Commercial Times.

2024-08-05

[News] Breaking Apple’s Monopoly – TSMC’s InFO Packaging Reportedly Adds Google Chips

TSMC’s fan-out (InFO) packaging process will no longer be exclusively used by Apple. According to a report from Commercial Times, it’s revealed that Google’s self-developed Tensor chips for their phones will switch to TSMC’s 3nm process next year and will also start using InFO packaging.

TSMC developed InFO packaging based on FOWLP (fan-out wafer-level packaging), which gained prominence after being adopted by the A10 processor in the iPhone 7 in 2016.

TSMC indicated that the current InFO_PoP technology has advanced to its ninth generation. Last year, it successfully certified 3nm chips, achieving higher efficiency and lower power consumption for mobile devices. The InFO_PoP technology, which features a backside redistribution layer (RDL), has entered mass production this year.

According to industry sources cited by the Commercial Times, Google will shift to TSMC for the Tensor G5 chips, which will be used in the Pixel 10 series next year. These chips will not only utilize the 3nm process but will also adopt integrated fan-out packaging.

This year’s Tensor G4 chips, set to be announced soon, use Samsung’s FOPLP (fan-out panel-level packaging). Although wafer-level packaging (WLP) is generally considered to have advantages over panel-level packaging (PLP), FOWLP still prevails at this stage due to yield and cost considerations.

TSMC has also begun developing FOPLP technology. Previously, per sources cited by a report from MoneyDJ, TSMC has officially formed a team, currently in the “Pathfinding” phase, and is planning to establish a mini line with a clear goal of advancing beyond traditional methods.

Although it is not expected to mature within the next three years, major customers like NVIDIA have partnered with foundry companies to develop new materials. One of TSMC’s major clients has already provided specifications for using glass materials.

Traditionally, chip advancements have been achieved through more advanced process nodes. However, new materials could enable the integration of more transistors on a single chip, achieving the same goal of scaling.

For instance, Intel plans to use glass substrates by 2030, potentially allowing a single chip to house one trillion transistors – 50 times the number in Apple’s A17 Pro processor. This suggests that glass substrates could become a significant milestone in chip development.

Another sources cited by Commercial Times have also indicated that glass substrates are part of the medium- to long-term technological roadmap. They can address challenges in large-size, high-density interconnect substrate development.

Currently, this technology is in the early stages of research and development. Its impact on ABF (Ajinomoto Build-up Film) substrates is expected to become significant in the second half of 2027 or later.

Read more

(Photo credit: TSMC)

Please note that this article cites information from Commercial Times and MoneyDJ.

2023-09-12

[News] Facing CoWoS Shortage, TSMC’s Taichung Plant Joins Capacity Support

According to a report by Taiwan’s Commercial Times, TSMC is facing a tight supply of advanced packaging capacity, with its Taichung factory ramping up equipment support at a rapid pace. Industry insiders have disclosed that TSMC’s annual production capacity for the backend CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging is only 150,000 to 300,000 units, falling short of customer demand by over 20%.

To address this shortfall, TSMC officially inaugurated its advanced packaging and testing Plant 6 in Zhunan in June. TSMC’s management has also committed to steadily increasing CoWoS production capacity each quarter, and third-party testing facilities are being actively engaged to bridge the gap.

It is worth noting that TSMC’s Longtan factory has traditionally been a key hub for CoWoS and InFO (Integrated Fan-Out) packaging, with a primary focus on InFO production at approximately 100,000 units per month and a smaller portion allocated to CoWoS. Although some of the InFO capacity has been relocated to the Southern Taiwan Science Park, Longtan’s physical space constraints continue to make Zhunan the primary location for CoWoS expansion. TSMC’s Taichung AP5 factory, on the other hand, is prioritizing WoS (Wafer-on-Substrate) expansion, with CoW (Chip-on-Wafer) expansion slated to commence next year. Many equipment suppliers have reportedly received urgent orders related to these expansion efforts.

Analysts estimate that this year’s overall CoWoS production will reach 110,000 units, doubling to 250,000 units next year. However, analysts caution that while TSMC currently dominates the CoWoS production landscape, other players are gradually entering the field. Therefore, it is crucial to monitor whether an oversupply situation may emerge in the mid-term next year.

(Photo credit: TSMC)

2023-08-11

Intel and Samsung Join TSMC in Fierce Advanced Packaging Race

As semiconductor process technology nears known physical limits, the spotlight among major industry players is shifting towards the development of advanced packaging. Concurrently, the rise of applications like artificial intelligence and AIGC has propelled the concept of advanced packaging into a new technological wave. In the midst of the semiconductor industry’s global competition, securing more orders has become a core objective for major players.

A Competitive Landscape in Advanced Packaging

The competition in advanced packaging technology is intensifying, with companies pouring substantial investments into the field, resulting in a landscape of vigorous competition. Various packaging technologies have emerged, with notable offerings from industry giants such as TSMC, Intel, and Samsung.

TSMC introduced 3DFabric, an integration of its TSMC-SoIC front-end technology with CoWoS and InFO back-end technologies, providing maximum flexibility for diverse innovative product designs.

Intel, on the other hand, features its 2.5D EMIB and 3D Foveros packaging technologies. EMIB is applied in the connection of logic chips and high-bandwidth memory, as seen in the Intel Xeon Max series and Intel Data Center GPU Max series.

Foveros allows top dies to overcome size limitations and accommodate more top and base dies, connected through copper pillars to reduce potential interference from through-silicon vias (TSVs).

Samsung also exhibits strong competitiveness in advanced packaging, with its 2.5D I-Cube4 and H-Cube, along with 3D X-Cube packaging technologies, achieving breakthroughs in multi-chip interconnects and integration.

Samsung’s I-Cube4, for example, integrates four HBM stack dies and one core compute IC on the silicon interposer layer, while H-Cube enhances packaging area through the stacking of HDI PCBs to accommodate designs with six or more HBM stack dies.

Advantages of the Three Giants

In recent years, the three semiconductor giants have directed substantial capital expenditure towards advanced packaging. Their diverse technological developments and marketing strategies are poised to ignite a global battle in the semiconductor advanced packaging industry.

TSMC holds the advantage with its dominant wafer process technology and an end-to-end comprehensive service approach. Coupled with Taiwan’s robust semiconductor ecosystem, TSMC leads the way in the advanced packaging domain.

Intel, while slightly trailing TSMC in advanced process technology, matches it in advanced packaging capabilities. Emphasizing flexible foundry services, Intel allows clients to mix and match its wafer manufacturing and packaging offerings. With manufacturing facilities scattered worldwide, Intel leverages geographic advantages, particularly in Western countries, to expand capacity and services, leading to anticipated gains in the future.

Samsung, like TSMC, offers end-to-end services, but its packaging technology lags behind TSMC’s. It secures a share in constrained supply situations. Notably, Samsung, in June 2022, was ahead of TSMC in unveiling the innovative GAA 3nm process, and is poised to combine it with 3D packaging technology, potentially marking a pivotal point in the next semiconductor generation.

With semiconductor technology’s continuous evolution and surging market demand, the competition among the three giants in advanced packaging will remain fierce. While wafer fabs currently prioritize processes, the next three to five years are expected to witness a gradual shift towards advanced packaging. Different packaging technologies and marketing strategies will ultimately determine companies’ positions and influence in the market.

(Photo credit: TSMC)

Read more:

  • Page 1
  • 2 page(s)
  • 6 result(s)

Get in touch with us