With advanced packaging capacity at TSMC being tight, the expansion of CoWoS has garnered significant attention. According to a report from Economic Daily News, Jun He, Vice President of Advanced Packaging Technology and Service at TSMC, noted at SEMICON Taiwan 2024 that the foundry giant is rapidly expanding its advanced packaging capacity to meet customer demands.

The company expects CoWoS capacity to grow at a compound annual growth rate of over 50% from 2022 to 2026, with high-speed expansion continuing at least until 2026.

During Jun He’s keynote at the “3D IC/CoWoS for AI Summit – HIGS Series Event” on September 4, He joked that due to severe supply shortages, he refrained from including numbers in his presentation, as customer complaints about insufficient capacity were frequent.

In response to strong customer demand, Jun He revealed that TSMC will continue to rapidly expand its advanced packaging capacity through 2026, with increased construction speeds. For CoWoS capacity, the time to build an advanced packaging plant has been reduced from three to five years to within two years, or even a year and a half.

He noted that the strong demand for advanced packaging is driven by the cost reduction benefits of chiplet design. The successful development of chiplets relies on advanced packaging, prompting TSMC to actively promote the 3DFabric Alliance to accelerate innovation and development within the 3D IC ecosystem.

Mike Hung, Senior Vice President of ASE echoed Jun He’s views, noting that the industry has learned valuable lessons from the 2.5D packaging sector since its mass production in 2013. ASE has been partnering with TSMC to boost their CoWoS capacities.

He added that further standardization of equipment or materials would be advantageous for accelerating industry innovation.

Take panel-level packaging as an example, he noted that while the technology could help  increased efficiency thanks to the transition from round to square substrates, it also presents challenges in areas like equipment and materials.

Jun He added that advancing packaging requires efforts from partners in advanced packaging materials and HBM to drive progress collectively.

On the other hand, DJ Lee, Director and COO of PCB leader ZDT Group, suggested that as the industry progresses, packaging substrates will trend towards higher layers, larger areas, flatness, and precise designs. To meet the semiconductor-level requirements, substrate manufacturers will need to enhance their smart manufacturing capabilities.

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(Photo credit: TSMC)

Amid the AI boom driving a surge in demand for advanced packaging, Samsung Electronics announced in March its ambition to achieve record-high revenue for the business this year, aiming to surpass the USD 100 million mark. The company, which is eager to catch up with TSMC not only on the foundry but also the advanced packaging business, was said to hire former TSMC deputy director Vic Lin as Vice President of the Advanced Packaging Business Unit in its semiconductor department. However, according to a report by ijiwei, the business unit has been disbanded recently, and rumor has it that Chinese semiconductor companies are attempting to recruit Lin.

It is worth noting that before joining TSMC, Lin worked at Micron Technology. Afterwards, during his 19-year tenure at TSMC from 1999 to 2017, Lin was responsible for the application of the semiconductor giant’s over 450 U.S. patents, the report notes. His major accomplishments included securing a major collaboration deal with Apple, as well as laying a solid foundation for TSMC’s expertise in 3D packaging technology.

Nowadays, the advanced packaging business has emerged as one of TSMC’s major growth momentum, with primary customer NVIDIA having the highest demand, occupying about half of the capacity, followed closely by AMD. As the demands for AI and HPC processors keep booming, TSMC revealed plans earlier to further expand its chip-on-wafer-on-substrate (CoWoS) capacity at a compound annual rate (CAGR) of over 60% until at least 2026, according to a report by AnandTech.

After leaving TSMC, Lin became the CEO of Skytech, where his extensive work experience helped him accumulate substantial expertise in packaging equipment manufacturing.

In 2022, Samsung established an Advanced Packaging Task Force, which was later transformed to its Advanced Packaging Business Team in 2023, of which Lin was said to join the team as Vice President, ijiwei notes.

However, industry insiders have revealed that the team was recently disbanded, and its members have returned to Samsung’s memory department and others, the report suggests. Additionally, Lin’s two-year contract with Samsung is said to be expire soon, and it seems unlikely that Samsung will renew it.

Being regarded as a “semiconductor packaging expert,” Lin’s next move is being closely watched. Certain Chinese semiconductor companies are rumored to get in contact with Lin, but it is expected that he will prioritize opportunities to collaborate with semiconductor companies in Taiwan, the report indicates.

The report notes that Samsung has confirmed that the team had been disbanded due to an internal organizational restructuring but declined to comment on personnel matters.

Earlier in May, as part of the restructuring process, the company has disbanded its Robot Business Team as well, which was responsible for developing its first wearable robot, “Bot Fit.”

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(Photo credit: Samsung)

According to sources cited in a report from Commercial Times, in response to the global increase in chip orders and rapid AI development, TSMC is actively seeking available land to keep its most advanced process technologies in Taiwan.

Currently, TSMC has already planned three 2nm fabs at the Nanzih Technology Industrial Park in Kaohsiung, southern Taiwan.

Regarding the need for additional land to accommodate facilities for more advanced nodes beyond 2nm, the report notes that the Kaohsiung City Government has been proactively preparing by evaluating land availability, as well as water and electricity supply, for TSMC’s next-generation advanced technology production, specifically targeting the A14 (14 angstrom) process.

Yet, regarding the matter, TSMC has remained discreet and declined to comment on market rumors regarding the progress of expansion.

Reportedly, the Nanzih Park site has the capacity to accommodate up to five fabs for TSMC, and there are rumors that its fourth and fifth fabs are likely to focus on A14 process, although TSMC has yet to confirm this.

TSMC’s first 2nm process fab in Nanzih is expected to begin mass production in 2025. Per sources cited by the report, the node will be used in high-performance computing (HPC), smartphones, electric vehicles, and autonomous driving applications.

Earlier, concerns were raised about the progress of TSMC’s CoWoS advanced packaging plant due to the discovery of cultural heritage sites at the Chiayi Science Park.

However, sources cited by Commercial Times have pointed out that while there have been some delays due to cultural heritage issues, TSMC’s adjustment plan has been approved. The company will adjust its working procedures in order to proceed with construction according to the original schedule, with no changes to the completion timeline.

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(Photo credit: TSMC)

According to a report from The Chosun Daily, major tech companies like NVIDIA are considering using Intel’s foundry services (IFS) as an alternative due to TSMC’s packaging capacity shortages. While packaging is a core competency for semiconductor foundries, Samsung, which is facing difficulties in attracting customers, will need to exert maximum effort to secure orders.

It’s highlighted by the report that the demand for AI accelerators is growing rapidly, but TSMC’s AI chip production capacity is unable to keep up.

Furthermore, per The Chosun Daily citing sources, major clients like NVIDIA and Apple have secured TSMC’s 3nm advanced process capacity, pushing order backlogs into 2026.

Therefore, major tech companies seeking alternatives are turning to Intel’s IFS. Since Intel’s Foveros is said to be comparable to TSMC’s CoWoS-S, it has made Intel’s advanced packaging a viable option to ensure supply.

TSMC and Intel offer advanced packaging services to customers under the names CoWoS and Foveros, respectively. Both CoWoS and Foveros are advanced packaging technologies that connect two or more semiconductor chips on a wafer and then place them onto a packaging substrate.

Reportedly, in addition to NVIDIA and Microsoft, Amazon and Cisco are considering outsourcing to Intel Foundry to reduce their dependence on TSMC.

The report further emphasizes that this market trend is likely to cause anxiety for Samsung, which competes with TSMC and Intel in advanced processes.

Recently, Samsung’s former clients, Google and Qualcomm, have chosen TSMC, while Intel, seen as a latecomer, is catching up by securing advanced packaging orders from major tech companies, potentially narrowing the gap with Samsung.

Kim Hak-sung, head of Hanyang Institute of Smart Semiconductor, said that packaging is a technology that critically influences customer acquisition in the AI semiconductor era, where various types of chips are interconnected.

He noted that although there may not be a substantial technical capabilities difference between Samsung Electronics and Intel, as mass production experience allows the process to stabilize and become more appealing to customers.

Kim eventually addressed that to stay competitive, Samsung needs to focus on capturing the volumes that TSMC cannot accommodate, positioning itself ahead of Intel.

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(Photo credit: Samsung)

Despite recent issues with NVIDIA’s GB200 shipments, the market remains optimistic about long-term AI demand, and CoWoS capacity continues to be in short supply.

According to a report from MoneyDJ, TSMC will assign orders of the initial stage of chip stacking in CoWoS packaging, Chip on Wafer (CoW), for the first time, to semiconductor assembly and test service provider SPIL.

The process will reportedly to manufactured at SPIL’s Zhong Ke Facility in Taichung. The company is said to build new capacity, with tool-in expected in the second quarter of 2025 and production ramping up in the third quarter.

TSMC President C.C. Wei previously disclosed that this year’s CoWoS capacity will more than double, with the growth trajectory similar in 2025. The company will continue to collaborate with OSATs to advance their packaging capabilities, Wei said.

Tien Wu, COO of another major outsourced semiconductor assembly & test services (OSAT) company ASE, also mentioned at its recent earnings call that the company has been co-developing both oS and CoW processes with their foundry partners for many years.

In fact, CoWoS is already a well-established technology. TSMC has been outsourcing the WoS (Wafer-on-Substrate) process, targeting small-batch, high-performance chips, while retaining the high-margin, high-tech CoW process in-house.

Lower-margin oS processes are handed over to packaging and testing companies. During the initial phase of this expansion wave, TSMC did not release CoW orders, but due to the overwhelming demand, they now have to outsource part of the process.

Industry sources cited by MoneyDJ further reveal that even Chinese companies have been excluded from the list, there are still several OSATs capable of handling TSMC’s outsourced CoWoS processes, such as Amkor, ASE, and SPIL.

After evaluation, SPIL’s plant in Central Taiwan was selected. It is reported that SPIL already collaborates with NVIDIA and AMD in the advanced packaging field, possessing capabilities not only for CoWoS-S but also for the higher-end CoWoS-L. This makes SPIL a strong second supplier for these major American companies.

Reportedly, TSMC will release the first phase of CoWoS-S orders to SPIL. Currently, SPIL’s CoWoS-related capacity is about 40,000 to 50,000 wafers per year. They plan to tool-in at the plant in Central Taiwan Science Park around the second quarter of next year.

It’s estimated by MoneyDJ’s report that TSMC’s CoWoS capacity remains in short supply, at 35,000 to 40,000 wafers per month this year. With the additional outsourced capacity, next year’s production could reach over 65,000 wafers per month, or possibly higher.

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(Photo credit: TSMC)