In response to the demands of high-performance computing, AI, 5G, and other applications, the shift towards chiplet and the incorporation of HBM memory has become inevitable for advanced chips. As a result, packaging has transitioned from 2D to 2.5D and 3D formats.

With chip manufacturing advancing towards more advanced process nodes, the model of directly packaging chips using advanced packaging technology from wafer foundries has emerged. However, this approach also signifies that wafer foundries will encroach upon certain aspects of traditional assembly and testing, leading to ongoing discussions about the ‘threat’ to traditional assembly and test firms since TSMC’s entry into advanced packaging in 2011.

But is this perspective accurate?

In fact, traditional assembly and test firms remain competitively positioned. Firstly, numerous electronic products still rely on their diverse traditional packaging techniques. Particularly, with the rapid growth of AIoT, electric vehicles, and drones, the required electronic components often still adopt traditional packaging methods. Secondly, faced with wafer foundries actively entering the advanced packaging domain, traditional assembly and test firms have not been idle, presenting concrete solutions to the challenge.

Advanced Packaging Innovations by Traditional Assembly and Test Firms

Since 2023, AI and AI server trends have rapidly emerged, driving the demand for AI chips. TSMC’s 2.5D advanced packaging technology, known as CoWoS, has played a pivotal role. However, the sudden surge in demand stretched TSMC’s capacity. In response, major traditional assembly and test firms such as ASE and Amkor have demonstrated their technical prowess and have no intention of being absent from this field.

For instance, ASE’s FOCoS technology enables the integration of HBM and ASIC. It restructures multiple chips into a fan-out module, which is then placed on the substrate, achieving the integration of multiple chips. Their FOCoS-Bridge technology, unveiled in May this year, utilizes silicon bridges (Si Bridge) to accomplish 2.5D packaging, bolstering the creation of advanced chips required for applications like AI, data centers, and servers.

Additionally, SPIL, a subsidiary of ASE, offers the FO-EB technology, a powerful integration of logic IC and HBM. As depicted below, this technology eschews silicon interposers, utilizing silicon bridges and redistribution layers (RDL) for connections, similarly capable of 2.5D packaging.

Another major player, Amkor, has not only collaborated with Samsung to develop the H-Cube advanced packaging solution but has also long been involved in ‘CoWoS-like technology.’ Through intermediary layers and through-silicon via (TSV) technology, Amkor can interconnect different chips, also possessing 2.5D advanced packaging capabilities.

China’s major assembly and test firm, Jiangsu Changjiang Electronics Technology (JCET), employs the XDFOI technology, integrating logic ICs with HBM through TSV, RDL, and microbump techniques, aimed at high-performance computing.

Given the recent surge in demand for high-end GPU chips, TSMC’s CoWoS capacity has fallen short, and NVIDIA is actively seeking support from second or even third suppliers. The ASE Group and Amkor have secured partial orders through their packaging technologies. This clearly illustrates that traditional assembly and test firms, even when faced with the entry of wafer foundries into the advanced packaging domain, still possess the capability to compete.

In terms of product types, wafer foundries focus on advanced packaging technology for major players like NVIDIA and AMD. Meanwhile, other products not in the highest-end category still opt for traditional assembly and test firms like ASE, Amkor, and JCET for manufacturing. Overall, with their presence in advanced packaging, as well as a hold on the expanding existing packaging market, traditional assembly and test firms continue to maintain their market competitiveness.

(Photo credit: Amkor)

Over the past few decades, semiconductor manufacturing technology has evolved from the 10,000nm process in 1971 to the 3nm process in 2022, driven by the need to increase the number of transistors on chips for enhanced computational performance. However, as applications like artificial intelligence (AI) and AIGC rapidly advance, demand for higher core chip performance at the device level is growing.

While process technology improvements may encounter bottlenecks, the need for computing resources continues to rise. This underscores the importance of advanced packaging techniques to boost the number of transistors on chips.

In recent years, “advanced packaging” has gained significant attention. Think of “packaging” as a protective shell for electronic chips, safeguarding them from adverse environmental effects. Chip packaging involves fixation, enhanced heat dissipation, electrical connections, and signal interconnections with the outside world. The term “advanced packaging” primarily focuses on packaging techniques for chips with process nodes below 7nm.

Amid the AI boom, which has driven demand for AI servers and NVIDIA GPU graphics chips, CoWoS (Chip-on-Wafer-on-Substrate) packaging has faced a supply shortage.

But what exactly is CoWoS?

CoWoS is a 2.5D and 3D packaging technology, composed of “CoW” (Chip-on-Wafer) and “WoS” (Wafer-on-Substrate). CoWoS involves stacking chips and then packaging them onto a substrate, creating a 2.5D or 3D configuration. This approach reduces chip space, while also lowering power consumption and costs. The concept is illustrated in the diagram below, where logic chips and High-Bandwidth Memory (HBM) are interconnected on an interposer through tiny metal wires. “Through-Silicon Vias (TSV)” technology links the assembly to the substrate beneath, ultimately connecting to external circuits via solder balls.

The difference between 2.5D and 3D packaging lies in their stacking methods. 2.5D packaging involves horizontal chip stacking on an interposer or through silicon bridges, mainly for combining logic and high-bandwidth memory chips. 3D packaging vertically stacks chips, primarily targeting high-performance logic chips and System-on-Chip (SoC) designs.

When discussing advanced packaging, it’s worth noting that Taiwan Semiconductor Manufacturing Company (TSMC), rather than traditional packaging and testing facilities, is at the forefront. CoW, being a precise part of CoWoS, is predominantly produced by TSMC. This situation has paved the way for TSMC’s comprehensive service offerings, which maintain high yields in both fabrication and packaging processes. Such a setup ensures an unparalleled approach to serving high-end clients in the future.

Applications of CoWoS

The shift towards multiple small chips and memory stacking is becoming an inevitable trend for high-end chips. CoWoS packaging finds application in a wide range of fields, including High-Performance Computing (HPC), AI, data centers, 5G, Internet of Things (IoT), automotive electronics, and more. In various major trends, CoWoS packaging is set to play a vital role.

In the past, chip performance was primarily reliant on semiconductor process improvements. However, with devices approaching physical limits and chip miniaturization becoming increasingly challenging, maintaining small form factors and high chip performance has required improvements not only in advanced processes but also in chip architecture. This has led to a transition from single-layer chips to multi-layer stacking. As a result, advanced packaging has become a key driver in extending Moore’s Law and is leading the charge in the semiconductor industry.

(Photo credit: TSMC)

According to media reports, in response to the booming demand in the artificial intelligence market, TSMC has altered its Kaohsiung factory plan. Originally scheduled for a 28-nanometer mature process, the factory will now be equipped with a 2-nanometer advanced process, with mass production expected to commence in the latter half of 2025. The official announcement of this factory plan is imminent.

During a investor conference held on July 20th, TSMC refrained from making any comments, citing the current quiet period. As reported by “Central News Agency,” Kaohsiung Mayor Chen Chi-mai expressed the city government’s respect for TSMC and pledged full assistance. However, it is worth noting that the 2-nanometer process requires more funding compared to the 28-nanometer process, and TSMC has already informed the Kaohsiung city government, seeking support in terms of water and power supply.

Official data indicates that TSMC’s 2-nanometer process offers a 10% to 15% performance improvement at the same power consumption or a 20% to 30% reduction in power consumption at the same performance level compared to the 3-nanometer process. The primary production base for the 2-nanometer process will be located in Hsinchu’s Baoshan area, with plans to construct four fabs. The trial production is scheduled for 2024, followed by mass production in the latter half of 2025.

(Photo credit: TSMC)

High Bandwidth Memory (HBM) is emerging as the preferred solution for overcoming memory transfer speed restrictions due to the bandwidth limitations of DDR SDRAM in high-speed computation. HBM is recognized for its revolutionary transmission efficiency and plays a pivotal role in allowing core computational components to operate at their maximum capacity. Top-tier AI server GPUs have set a new industry standard by primarily using HBM. TrendForce forecasts that global demand for HBM will experience almost 60% growth annually in 2023, reaching 290 million GB, with a further 30% growth in 2024.

TrendForce’s forecast for 2025, taking into account five large-scale AIGC products equivalent to ChatGPT, 25 mid-size AIGC products from Midjourney, and 80 small AIGC products, the minimum computing resources required globally could range from 145,600 to 233,700 Nvidia A100 GPUs. Emerging technologies such as supercomputers, 8K video streaming, and AR/VR, among others, are expected to simultaneously increase the workload on cloud computing systems due to escalating demands for high-speed computing.

HBM is unequivocally a superior solution for building high-speed computing platforms, thanks to its higher bandwidth and lower energy consumption compared to DDR SDRAM. This distinction is clear when comparing DDR4 SDRAM and DDR5 SDRAM, released in 2014 and 2020 respectively, whose bandwidths only differed by a factor of two. Regardless of whether DDR5 or the future DDR6 is used, the quest for higher transmission performance will inevitably lead to an increase in power consumption, which could potentially affect system performance adversely. Taking HBM3 and DDR5 as examples, the former’s bandwidth is 15 times that of the latter and can be further enhanced by adding more stacked chips. Furthermore, HBM can replace a portion of GDDR SDRAM or DDR SDRAM, thus managing power consumption more effectively.

TrendForce concludes that the current driving force behind the increasing demand is AI servers equipped with Nvidia A100, H100, AMD MI300, and large CSPs such as Google and AWS, which are developing their own ASICs. It is estimated that the shipment volume of AI servers, including those equipped with GPUs, FPGAs, and ASICs, will reach nearly 1.2 million units in 2023, marking an annual growth rate of almost 38%. TrendForce also anticipates a concurrent surge in the shipment volume of AI chips, with growth potentially exceeding 50%.

According to TrendForce, the global quantum computing market was valued at US$470 million in 2021, an increase of 16.7% compared to 2020. This market is mainly led by China and the United States, driving global quantum computing and its technological progress, especially in upper-layer software. In terms of algorithmic speed, small-scale problems have been put to the test through experimentation. The market is expected to reach US$580 million in 2022, with an annual growth rate of approximately 18.8%, and current growth rate expanding every year until 2027.

According to TrendForce, as stated in the Chinese government’s plan for software and information technology services, its quantum technology policy will be further implemented from a national level to departments including national defense, industry, and technology and more targeted policies will be released through tiered departmental levels such as for AI, quantum information technology, biotechnology, semiconductors, and autonomous systems. To this end, the Chinese government is establishing relevant laboratories in Beijing, Shanghai, and Hefei to promote the rapid development of quantum technology and quantum computing cloud platforms.

When China launched its “Five-Year Plan” in 2006 to promote economic and industrial development, it also focused on the development of quantum science and technological breakthroughs, as well as the deeply integrated development and application of quantum computing in emerging technologies such as AI, edge computing, big data, IoT, and cloud such as advanced space quantum communication technology and quantum computing combined with AI/ML, IoT, and cloud, providing assistance to the Chinese Academy of Sciences’ quantum satellites, the University of Science and Technology of China’s quantum computer, and other quantum processors to achieve breakthroughs in technology and functional characteristics. Therefore, the cumulative investment in China’s quantum field is estimated to reach US$15 billion in 2022.

Main applications of China’s quantum computing market

Considering the immense size, extremely harsh operating environment, and high price of quantum computers, quantum computing applications are rapidly developing towards cloud platforms. Therefore, research on quantum computers primarily focus on four types of applications: simulation, optimization, cryptography, and machine learning. “Simulation” is most used in processes that occur in nature such as weather forecasting, mid- and long-term climate deductions, and polar climate change. It is also widely used in fluid mechanics, drug discovery, battery design, and high-frequency trading, derivatives, and options pricing in the financial industry.

“Optimization” is the use of quantum algorithms to determine the best solution among a set of feasible options and is mostly used for risk management in traffic arteries, logistics, self-driving navigation systems, and financial investment portfolios. “Machine learning” is used to identify patterns in data and statistics, enhance the training of machine learning algorithms, accelerate AI development, and introduced to self-driving cars and financial systems to prevent fraud and money laundering.

As enumerated above, the scope of quantum computing applications is gradually expanding, covering fields including supply chain, finance, transportation, logistics, pharmaceuticals, chemicals, automobiles, aviation, energy, and meteorology. Sectors such as pharmaceuticals, chemicals, and new materials use quantum operations to analogize molecular properties, directly analyze and obtain large molecular properties through a computerized digital format, shorten the time for theoretical verification, and thereby accelerating drug research and development and the development of new materials.

In the automotive field, in order to accelerate the promotion of electrification strategies, major carmakers have applied quantum computing to chemical analogies and are committed to developing batteries with better performance. In the aerospace field, quantum computing is used to solve some of the most difficult challenges facing the aviation industry, from basic materials, product research and development, machine learning optimization, to complex system optimization, and are even changing the way aircraft are made and fly.

（Image credit: Pixabay）