In recent developments, Samsung Foundry, a subsidiary of Samsung Electronics, has disclosed that it has initiated discussions with major chip clients, gearing up to provide services utilizing 1.4nm and 2nm processes.

It’s been said that Samsung being ahead in the production of 3nm GAA (gate-all-around) process, yet not as favored by major clients as TSMC. In response to the comment, Ki-tae Jeong, the CTO of Samsung Foundry, had share his insights at Semiconductor Expo 2023 in South Korea.

According to the Chosun Ilboon’s report, Jeong pointed out that in the semiconductor foundry industry, it typically takes approximately 3 years for major clients to make their final purchasing decisions. Samsung is actively engaging with prominent clients, and results may become evident in the coming years. Also, the company is currently discussing future processes such as 2nm and 1.4nm with major clients.

How are advanced semiconductor processes progressing?

Compared to mature processes, advanced processes are better suited for applications that demand high performance and low power consumption. With emerging technologies like AI and high-performance computing driving the industry, the demand for advanced processes continues to rise. Leading semiconductor companies are committed to developing new technologies, with chip advanced processes evolving from 5nm to 4nm and now down to 3nm, while looking ahead to the possibility of reaching 2nm and 1.4nm.

Current progress from major players:

Samsung
Samsung has already commenced mass production of its second-generation 3nm chips and aims to introduce the 2nm process by the end of 2025, with the 1.4nm process expected by the end of 2027.

TSMC
TSMC is planning to start production for N3P in the latter half of 2024, with N3X and the 2nm process set to enter mass production in 2025. TSMC will introduce Gate-all-around FETs (GAAFET) transistors for the first time at the 2nm process node, offering a 15% speed increase at the same power consumption and up to a 30% reduction in power consumption at the same speed, all while increasing chip density by more than 15%.

Intel
Intel is diligently pursuing its “Four Years, Five Nodes” plan. Presently, Intel 7 and Intel 4 are in mass production, and the Intel 3 process is expected to enter the readiness for production stage in the latter half of this year. Subsequently, Intel 20A and 18A processes are planned to enter the readiness for production stage in the first and second halves of 2024, respectively.

Moreover, industry experts believe that in the near term, Intel will focus on the Intel 3 process as its flagship offering in the advanced process semiconductor foundry sector to compete with TSMC, Samsung, and other players.

According to TrendForce’s latest investigation, Chinese foundries have already suspended plans to expand production capacity for advanced processes after the US government began restricting the exportation of equipment and technical support for processes related to non-planar architectures. TrendForce believes that a further tightening of the restrictions on lithography equipment will mainly affect mature processes, especially the 28nm. Chinese foundries might proceed more slowly in adding new production capacity or raising output for the 28nm process due to the prolonged reviews on their equipment purchases.

TrendForce semiconductor analyst, Joanne Chiao, said that Chinese semiconductor companies have already suspended the development of chips featuring the GAA architecture (i.e., nodes that are generally ≤3nm) after the US government began restricting the exportation of EDA tools and related technical support. If we talk about the FinFET architecture that Chinese foundries are able to produce for now, it is possible to achieve the faster computing speed of the more advanced chips by combining multiple lower-end chips. However, it might also be very challenging to raise the production yield rate of a solution that integrates multiple chips, not to mention that the power consumption of such solution might be very high as well.

Seeing the US export control, for now, US government has not imposed restrictions on the exportation of technical support for processes related to planar architectures. On the other hand, Chinese foundries might halt their advanced chip (14nm) production at any time if they encounter an equipment malfunction or another problem that requires technical support from US equipment providers.

At last, Chiao emphasized that the US sanction has definitely accelerated the development of an “all-China” semiconductor manufacturing supply chain. Nevertheless, the world’s top eight semiconductor equipment providers all come from Japan or the US. From the perspective of the foundry industry, it will be hard for China to realize a wholly or mostly native semiconductor supply chain within the foreseeable future.

The market started worrying about the oversupply in semiconductor 2023, when the demand will start growing again depends on two factors: the situation of the macroeconomy and the inventory status.

Since foundries’ capacity utilization rates started drop in 3Q22, chip supply as a whole has decreased significantly. This, in turn, has helped limit inventory growth across the supply chain. However, the global economy is still at risk of a mild recession, so consumers may allocate more of their spending to daily necessities. They may also spend more on tourism due to easing of the pandemic. This could lead to weak sales for consumer electronic products.

Not to mention that most consumers already purchased the electronic products that they need for working or studying at home during the pandemic. Assuming that the overall inventory level of the supply chain will return to a healthier level, TrendForce believes that chip demand will begin to rebound to a certain extent in 2Q23. Then, the demand growth will become more obvious from 3Q23 onward. Nevertheless, this demand growth may not be too strong due to uncertainties in the global economy.

If we observe the situation from the perspective of the foundry industry, smartphones represent the largest application segment in terms of wafer consumption. The smartphone supply chain started inventory correction earlier, so demand rebound might be more obvious initially for smartphone-related chips compared with chips used in other consumer devices. On the other hand, with different benchmarks, the demand for HPC chips will show more significant growth compared with the demand for smartphone chips.

Although current semiconductor process technologies have evolved to the 3nm and 5nm nodes, SoC (system on a chip) architecture has yet to be manufactured at these nodes, as memory and RF front-end chiplets are yet to reach sufficient advancements in transistor gate length and data transmission performance. Fortunately, EDA companies are now attempting to leverage heterogeneous integration packaging technologies to link the upstream and downstream semiconductor supply chains as well as various IP cores. Thanks to this effort, advanced packaging technologies, including 2.5D/3D IC and SiP, will likely continue to push the limits of Moore’s Law.

While SoC development has encountered bottlenecks, EDA tools are the key to heterogeneous integration packaging

As semiconductor process technologies continue to evolve, the gate length of transistors have also progressed from μm (micrometer) nodes to nm (nanometer) nodes. However, the more advanced process technologies are not suited for manufacturing all semiconductor components, meaning the development of SoC architectures has been limited as a result. For instance, due to physical limitations, memory products such as DRAM and SRAM are mostly manufactured at the 16nm node at the moment. In addition, RF front-end chiplets, such as modems, PA (power amplifiers), and LNA (low noise amplifiers) are also primarily manufactured at the 16nm node or other μm nodes in consideration of their required stability with respect to signal reception/transmission.

On the whole, the aforementioned memory, and other semiconductor components cannot be easily manufactured with the same process technologies as those used for high-end processors (which are manufactured at the 5nm and 3nm nodes, among others). Hence, as the current crop of SoCs is not yet manufactured with advanced processes, EDA companies including Cadence, Synopsys, and Siemens (formerly Mentor) have released their own heterogeneous integration packaging technologies, such as 2.5D/3D IC and SiP (system in package), in order to address the demand for high-end AI, SoC architecture, HPC (high performance computing), and optical communication applications.

EDA companies drive forward heterogeneous integration packaging as core packaging architecture and integrate upstream/downstream supply chain

Although the current crop of high-end semiconductor process technologies is still incapable of integrating such components as memory, RF front-end, and processors through an SoC architecture, as EDA companies continue to adopt heterogeneous integration packaging technology, advanced packaging technologies, including 2.5D/3D IC and SiP, will likely extend the developmental limitations of Moore’s Law.

Information presented during Semicon Taiwan 2021 shows that EDA companies are basing their heterogeneous integration strategies mainly on the connection between upstream and downstream parts of the semiconductor supply chain, in addition to meeting their goals through chip packaging architectures. At the moment, significant breakthroughs in packaging technology design and architecture remain unfeasible through architectural improvements exclusively. Instead, companies must integrate their upstream chip design and power output with downstream substrate signal transmission and heat dissipation, as well as other factors such as system software and use case planning. Only by integrating the above factors and performing the necessary data analysis can EDA companies gradually evolve towards an optimal packaging architecture and in turn bridge the gap of SoC architectures.

With regards to automobiles (including ICE vehicles and EVs), their autonomous driving systems, electronic systems, and infotainment systems require numerous and diverse semiconductor key components that range from high-end computing chips to mid-range and entry-level MCUs. As such, automotive chip design companies must carefully evaluate their entire supply chain in designing automotive chip packages, from upstream manufacturers to downstream suppliers of substrates and system software, while also keeping a holistic perspective of various use cases. Only by taking these factors into account will chip design companies be able to respond the demands of the market with the appropriate package architectures．

（Image credit: Pexels）

As UMC and GlobalFoundries successively end their respective developments of advanced processes, the advanced process market has now become an oligopoly, with TSMC and Samsung as the only remaining suppliers （excluding SMIC, which is currently affected by geopolitical tensions between China and the US）. According to TrendForce’s latest investigations, TSMC holds a 70% market share in advanced processes below – and including – the 1Xnm node, while Samsung’s market share is about 30%.

As electronic products demand faster data transmission speeds and better performance in response to IoT and 5G applications, the chips contained in these products also need to shrink in size and consume less power. Hence, process technologies need to evolve in order to enable the production of increasingly advanced chips. In this light, suppliers of such chips as smartphone AP, CPU, and GPU primarily rely on Taiwan for its semiconductor industry’s advanced process technologies.

Why is Taiwan able to hold key manufacturing competencies, market shares, and unsurpassed technologies in the global foundry industry?

After TSMC pioneered its pure-play foundry services more than 30 years ago, UMC also subsequently transitioned to a foundry business model. However, the build-out and maintenance of wafer fabs require enormous human resources, capital expenditures, and environmental support, all of which have been skyrocketing since the industry progressed below the 40nm node into the EUV era. Factors including governmental support, human resource development, utility services, and long-term amortization and depreciation are all indispensable for foundries to keep up their fab operations. TrendForce’s findings indicate that Taiwan possesses about 50% of the global foundry capacity, and this figure will likely continue growing due to the persistent demand for advanced processes.

Taiwanese foundries led by TSMC and UMC operate based on a pure-play foundry model, which means they do not compete with their clients outside of foundry operations. Foundries are able to maximize the profitability of the semiconductor ecosystem in Taiwan thanks to Taiwan’s comprehensive PC, ICT, and consumer electronics industries.

In addition, not only are they able to deliver PPA（performance, power, and area） advantages to their clients through technology scaling and node shrinking, they are also unsurpassed in their comprehensive silicon IP cores and longstanding product development services. Other competing foundries are unlikely to make breakthroughs in these fields and catch up to Taiwanese foundries in the short run.

On the whole, the Taiwanese foundry industry is able to maintain its leadership thanks to competencies in human capital, client strategies, process technologies, capital intensify, economies of scale, and superior production capacities.

Furthermore, not only do advancements in semiconductor fabrication technology require developmental efforts from foundries, but they also need support throughout the entire supply chain, including upstream wafer suppliers and downstream client feedbacks, both of which can serve to eliminate yield detractors and raise yield rates. Therefore, the Taiwanese semiconductor industry derives its advantage from foundries（TSMC, UMC, PSMC, and VIS）, as well as from the cross-industrial support across silicon wafer suppliers（SAS and GlobalWafers）, fabless IC design clients, and packaging and testing operators（ASE, etc.）

（Cover image source: TSMC）