[News] MediaTek Reportedly Adopts Dual Packaging Strategy With Intel EMIB, TSMC CoWoS for AI ASIC Push

As TSMC’s CoWoS capacity crunch continues, Intel’s EMIB has emerged as a strong alternative, with IC design leader MediaTek reportedly adopting a dual advanced packaging strategy. According to Commercial Times, MediaTek is accelerating its expansion into AI ASICs and data center markets, while industry sources say the company is deepening cooperation with TSMC on CoWoS and SoIC while also introducing Intel’s EMIB technology for ASIC chips targeting specific customers, providing future clients with more diversified options.

MediaTek said demand for AI infrastructure remains extremely strong, with packaging now a critical part of the solution. As a result, the company said it must invest in multiple packaging technologies to address diverse customer needs. Supply chain sources say MediaTek sees significant value in EMIB, with execution progress reportedly advancing smoothly.

Notably, MediaTek recently appointed former TSMC R&D and advanced packaging executive Douglas Yu as a part-time advisor. According to the report, the move will not only deepen cooperation with TSMC on CoWoS and SoIC, but also strengthen MediaTek’s capabilities in next-generation ASIC and AI infrastructure packaging technologies.

As noted by The Journalist, industry analysts believe the strategy could help MediaTek secure greater priority access to CoWoS capacity while positioning the company ahead of its projected AI ASIC shipments in 2028, when its market share is estimated to reach 26%, or nearly 5 million units.

The strategy is expected to be reflected in upcoming AI chip projects. According to Commercial Times, Google’s next-generation TPU 8 architecture will include the TPU 8t for training and TPU 8i for inference. MediaTek is reportedly involved in the core design of the training-focused TPU 8t, which will use TSMC’s N3P process and CoWoS-S advanced packaging technology for its AI ASIC, while the TPU v8e is expected to adopt Intel’s EMIB technology.

EMIB Emerges as CoWoS Alternative for AI ASICs

According to TrendForce, Intel’s EMIB offers several advantages over TSMC’s CoWoS, including eliminating the need for a large interposer through embedded silicon bridges, improving manufacturing yield, reducing warpage risk, and enhancing long-term reliability. EMIB also supports larger effective reticle-size scaling, with EMIB-M already reaching 6× and projected to achieve 8–12× by 2026–2027, compared with CoWoS-S at 3.3× and CoWoS-L at around 3.5× today.

However, TrendForce notes that EMIB’s limited bridge area and routing density can constrain bandwidth and increase latency versus CoWoS, making it more suitable for ASICs than high-bandwidth, ultra-low-latency GPUs.

Read more

• [News] SK hynix Reportedly Tests Intel EMIB 2.5D Packaging With HBM Amid TSMC CoWoS Tightness
• [News] Intel’s EMIB Reportedly Gains Traction at Google, Meta; Yields Said to Reach ~90% Milestone

(Photo credit: MediaTek)