As silicon photonics has become a key technology in the AI era, semiconductor giants, including Intel and TSMC, have joined the battlefield. Now another tech giant has engaged in the war, while U.S. chip giant AMD is reportedly seeking silicon photonics partners in Taiwan, according to local media United Daily News.

According to the report, AMD has reached out to Taiwanese rising stars in the sector, including BE Epitaxy Semiconductor and best Epitaxy Manufacturing Company. The former focuses on the design, research and development of silicon photonics platforms, while the latter possesses MOCVD machines to produce 4-inch and 6-inch epitaxy wafers.

Regarding the rumor, AMD declined to comment. Recently, the AI chip giant announced a USD 4.9 billion acquisition of server manufacturer ZT Systems to strengthen its AI data center infrastructure, with the aim to further enhance its system-level R&D capability. Now it seems that AMD is also eyeing to set foot in the market, as silicon photonics is poised to be a critical technology in the future.

Earlier in July, AMD is said to establish a research and development (R&D) center in Taiwan, which will focus on several advanced technologies, including silicon photonics, artificial intelligence (AI), and heterogeneous integration.

Here’s why the technology matters: As chipmakers keep pushing the boundaries of Moore’s Law, leading to increased transistor density per unit area, signal loss issues inevitably arise during transmission since chips rely on electricity to transmit signals. Silicon photonics technology, on the other hand, by replacing electrical signals with optical signals for high-speed data transmission, successfully overcomes this challenge, achieving higher bandwidth and faster data processing.

On September 3, a consortium of more than 30 companies, including TSMC, announced the establishment of the Silicon Photonics Industry Alliance (SiPhIA) at SEMICON.

According to a previous report by Nikkei, TSMC and its supply chain are accelerating the development of next-generation silicon photonic solutions, with plans to have the technology ready for production within the next three to five years.

AMD’s major rival, NVIDIA, is reportedly collaborating with TSMC to develop optical channel and IC interconnect technologies.

On the other hand, Intel has been developing silicon photonics technology for over 30 years. Since the launch of its silicon photonics platform in 2016, Intel has shipped over 8 million photonic integrated circuits (PICs) and more than 3.2 million integrated on-chip lasers, according to its press release. These products have been adopted by numerous large-scale cloud service providers.

Interestingly enough, Intel has also been actively collaborating with Taiwanese companies in the development of silicon photonics, United Daily News notes. One of its most notable partners is LandMark Optoelectronics, which supplies Intel with critical upstream silicon photonics materials, such as epitaxial layers and related components.

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(Photo credit: AMD)

If you happen to be a technology enthusiast, June would certainly be a month to watch. NVIDIA CEO Jensen Huang, joined by AMD CEO Lisa Su, visited Taiwan to announce their product roadmaps in COMPUTEX 2024. NVIDIA unveiled its new generation Rubin architecture, indicating that the R series products are expected to go into mass production in the fourth quarter of 2025.

On the other hand, AMD introduced its Ryzen AI 300 Series processors with the world’s most powerful Neural Processing Unit (NPU) for next-gen AI PCs, featuring a new Zen 5 CPU, as well as its latest AI chips, MI325X and MI350.

Interestingly enough, on 4 June, the world’s largest semiconductor foundry, TSMC, held its shareholders’ meeting in Hsinchu, Taiwan. When asked about the company’s relationships with NVIDIA and AMD, President C.C. Wei has reaffirmed TSMC’s strong relationships with the two tech giants, saying that the company will prosper with its clients.

What will be the highlights for TSMC’s progress in advanced logic process, and what are some of the most advanced products introduced in COMPUTEX made with TSMC’s advanced nodes? Please proceed to find out more. For now, TSMC’s 3nm seems to be the most popular node.

N3 Family

TSMC’s N3E (the more cost-effective second generation of the 3nm process) entered mass production in the fourth quarter of 2023. On the other hand, N3P (a more advanced version) is scheduled to enter mass production in the second half of 2024. Its yield performance is close to that of N3E, while customer product designs have already been tape-out.

TSMC states that due to N3P’s superior performance, better power consumption and area (PPA) characteristics, most 3nm products will eventually adopt the node. In the future, the industry may expect to see more high-end products manufactured with 3nm.

Regarding capacity, driven by the strong demand from HPC and mobile phone, TSMC has tripled its 3nm capacity in 2024 compared to that of 2023. However, as it is still not enough, the world’s largest semiconductor foundry has been striving to meet customer demand.

Intel’s Lunar Lake/ Arrow Lake

At COMPUTEX 2024, Intel CEO Pat Gelsinger introduced Lunar Lake, its latest AI PC chip, and thank its friend “TSMC” for their full support.

Starting Q3 2024 in time for the holiday season, Lunar Lake will power more than 80 new laptop designs across more than 20 original equipment manufacturers.

In a previous report by Wccftech, Gelsinger stated that Intel has collaborated with TSMC to power up its next-gen CPUs, adopting N3B, the first-generation 3nm process, for Lunar Lake and Arrow Lake.

NVIDIA’s Rubin

On the other hand, NVIDIA’s Rubin GPU architecture is now official: the Rubin GPU will feature 8 HBM4, while the Rubin Ultra GPU will come with 12 HBM4 chips, noted by Jensen Huang, CEO of NVIDIA.

Per a report from Wccftech, NVIDIA’s Rubin GPU is expected to utilize TSMC’s CoWoS-L packaging technology, along with its N3 process. Moreover, NVIDIA will use next-generation HBM4 DRAM to power its Rubin GPU.

Regarding NVIDIA’s previous GPUs, according to Commercial Times’ report, H200 and B100 reportedly are said to adopt TSMC’s 4-nanometer and 3-nanometer processes, respectively.

AMD’s MI 325X/ MI350

On 3 June, AMD CEO Lisa Su stated that the company’s relationship with TSMC is “very strong,” even as rumors have been circulating about a potential partnership with Samsung, TSMC’s main competitor.

AMD unveiled the company’s latest AI chip, MI325X, at the opening of COMPUTEX Taipei. Su emphasized that the MI325X boasts 30% faster computing speed compared to NVIDIA’s H200.

Furthermore, she also announced that AMD will release MI350 in 2025, which will be manufactured with TSMC’s 3nm process, while MI400 is expected to follow, launched in 2026.

When asked if AMD intended to procure chips manufactured using Samsung’s 3-nanometer (3nm) gate-all-around (GAA) process, Su reiterated AMD’s commitment to utilizing “the most advanced technology,” saying that AMD is certainly going to use 3 nm, 2 nm, and beyond. She also confirmed that there are several 3nm products currently being developed in collaboration with TSMC.

In addition to TSMC’s collaboration with clients on 3nm, this article also curates TSMC’s progresses on its 2nm node and other advanced processes. More information below:

N2 Family

The N2 process utilizes nanosheet transistors, thus would be able to offer superior energy efficiency. Currently, TSMC’s 2nm technology is progressing smoothly, with nanosheet conversion performance reaching the target of 90%, indicating that the yield exceeds 80%. Mass production is expected in 2025.

In the future, TSMC states that more members of the N2 family will emerge, including applications like N2P and N2X.

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(Photo credit: TSMC)

TSMC today unveiled its newest semiconductor process, advanced packaging, and 3D IC technologies for powering the next generation of AI innovations with silicon leadership at the Company’s 2024 North America Technology Symposium.

TSMC debuted the TSMC A16TM technology, featuring leading nanosheet transistors with innovative backside power rail solution for production in 2026, bringing greatly improved logic density and performance. TSMC also introduced its System-on-Wafer (TSMC-SoW™) technology, an innovative solution to bring revolutionary performance to the wafer level in addressing the future AI requirements for hyperscaler datacenters.

“We are entering an AI-empowered world, where artificial intelligence not only runs in data centers, but PCs, mobile devices, automobiles, and even the Internet of Things,” said TSMC CEO Dr. C.C. Wei. “At TSMC, we are offering our customers the most comprehensive set of technologies to realize their visions for AI, from the world’s most advanced silicon, to the broadest portfolio of advanced packaging and 3D IC platforms, to specialty technologies that integrate the digital world with the real world.”

New technologies introduced at the symposium include:

TSMC A16TM Technology: With TSMC’s industry-leading N3E technology now in production, and N2 on track for production in the second half of 2025, TSMC debuted A16, the next technology on its roadmap.

A16 will combine TSMC’s Super Power Rail architecture with its nanosheet transistors for planned production in 2026. It improves logic density and performance by dedicating front-side routing resources to signals, making A16 ideal for HPC products with complex signal routes and dense power delivery networks.

Compared to TSMC’s N2P process, A16 will provide 8-10% speed improvement at the same Vdd (positive power supply voltage), 15- 20% power reduction at the same speed, and up to 1.10X chip density improvement for data center products.

TSMC NanoFlexTM Innovation for Nanosheet Transistors: TSMC’s upcoming N2 technology will come with TSMC NanoFlex, the company’s next breakthrough in design-technology co optimization. TSMC NanoFlex provides designers with flexibility in N2 standard cells, the basic building blocks of chip design, with short cells emphasizing small area and greater power efficiency, and tall cells maximizing performance. Customers are able to optimize the combination of short and tall cells within the same design block, tuning their designs to reach the optimal power, performance, and area tradeoffs for their application.

N4C Technology: Bringing TSMC’s advanced techynology to a broader range of of applications, TSMC announced N4C, an extension of N4P technology with up to 8.5% die cost reduction and low adoption effort, scheduled for volume production in 2025.

N4C offers area-efficient foundation IP and design rules that are fully compatible with the widely-adopted N4P, with better yield from die size reduction, providing a cost-effective option for value-tier products to migrate to the next advanced technology node from TSMC.

CoWoS, SoIC, and System-on-Wafer (SoW): TSMC’s Chip on Wafer on Substrate (CoWoS) has been a key enabler for the AI revolution by allowing customers to pack more processor cores and high-bandwidth memory (HBM) stacks side by side on one interposer. At the same time, our System on Integrated Chips (SoIC) has established itself as the leading solution for 3D chip stacking, and customers are increasingly pairing CoWoS with SoIC and other components for the ultimate system-in-package (SiP) integration.

With System-on-Wafer, TSMC is providing a revolutionary new option to enable a large array of dies on a 300mm wafer, offering more compute power while occupying far less data center space and boosting performance per watt by orders of magnitude.

TSMC’s first SoW offering, a logic only wafer based on Integrated Fan-Out (InFO) technology, is already in production. A chip-on-wafer version leveraging CoWoS technology is scheduled to be ready in 2027, enabling integration of SoIC, HBM and other components to create a powerful wafer-level system with computing power comparable to a data center server rack, or even an entire server.

Silicon Photonics Integration: TSMC is developing Compact Universal Photonic Engine (COUPE ) technology to support the explosive growth in data transmission that comes with the AI boom. COUPE uses SoIC-X chip stacking technology to stack an electrical die on top of a photonic die, offering the lowest impedance at the die-to-die interface and higher energy efficiency than conventional stacking methods.

TSMC plans to qualify COUPE for small form factor pluggables in 2025, followed by integration into CoWoS packaging as co-packaged optics (CPO) in 2026, bringing optical connections directly into the package.

Automotive Advanced Packaging: After introducing the N3AE “Auto Early” process in 2023, TSMC continues to serve our automotive customers’ needs for greater computing power that meets the safety and quality demands of the highway by integrating advanced silicon with advanced packaging.

TSMC is developing InFO-oS and CoWoS-R solutions for applications such as advanced driver assistance systems (ADAS), vehicle control, and vehicle central computers, targeting AEC-Q100 Grade 2 qualification by fourth quarter of 2025.

(Photo credit: TSMC)

As generative AI applications fuel the era of high computing power, Foxconn’s connector subsidiary FIT announced on March 25th a cross-industry collaboration with MediaTek. Together, they will develop next-generation high-speed connectivity solutions, specifically Co-Packaged Optics (CPO), aiming to capitalize on the booming silicon photonics market.

According to a report from Economic Daily News, FIT and MediaTek have previously collaborated as upstream and downstream partners, with FIT being a leading manufacturer of custom ASIC sockets and having significant capacity for cooperation with upstream IC design firms.

This collaboration may mark their first joint venture in developing next-generation optical communication products, aiming to create CPO high-speed connectivity solutions using ASIC platforms and silicon photonics technology.

Foxconn Group Collaborates with MediaTek Across Industries

Industry sources cited by the report suggest that traditional data center transmission occurs on PCBs, whereas the CPO architecture is situated on the substrate, integrating optical communication components with switch into a module installed in a slot. This configuration shortens data transmission paths, reducing transmission losses and power consumption.

With the commercialization of generative AI, large language models require extensive computation within data centers, demanding high transmission rates to enhance operational efficiency. Traditional data transmission methods face significant signal loss, prolonging model training times and increasing power consumption. Consequently, the emergence of new network communication technology, CPO, addresses these challenges.

FIT asserts that CPO represents the next-generation optical communication transmission architecture, capable of shortening transmission paths, reducing transmission losses and signal delays, thereby providing more robust connectivity for AI computing and applications. It can be combined with the company’s existing optical communication products of 800G and 1.6T, forging ahead with next-generation network communication technology.

Through collaboration with MediaTek, they aim to offer customers more diverse and efficient connectivity solutions, driving the development of the era of high computational power.

MediaTek, as per the report, emphasized its commitment to adopting the industry’s most advanced processes, packaging technologies, and architectures, providing customers with diverse ASIC design platforms.

This initiative aims to offer the latest and comprehensive solutions to the rapidly growing data center and server markets. Collaborating with FIT on CPO further enhances their ability to deliver next-generation high-speed transmission solutions, thereby creating new market opportunities for customers.

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(Photo credit: Foxconn)

MediaTek has reportedly made its foray into the booming field of Heterogeneous Integration Co-Packaged Optics (CPO), announcing on March 20th a partnership with optical communications firm Ranovus to launch a customized Application-Specific Integrated Circuit (ASIC) design platform for CPO. This platform is reported to provide advantages such as low cost, high bandwidth density, and low power consumption, expanding MediaTek’s presence in the thriving markets of AI, Machine Learning (ML), and High-Performance Computing (HPC).

According to its press release, on the eve of the 2024 Optical Fiber Communication Conference (OFC 2024), MediaTek announced the launch of a new-generation customized chip design platform, offering heterogeneous integration solutions for high-speed electronic and optical signal transmission interfaces (I/O).

MediaTek stated that it will be demonstrating a serviceable socketed implementation that combines 8x800G electrical links and 8x800G optical links for a more flexible deployment. It integrates both MediaTek’s in-house SerDes for electrical I/O as well as co-packaged Odin® optical engines from Ranovus for optical I/O.

As per the same release, leveraging the heterogeneous solution that includes both 112G LR SerDes and optical modules, this CPO demonstration is said to be delivering reduced board space and device costs, boosts bandwidth density, and lowers system power by up to 50% compared to existing solutions.

MediaTek emphasizes that its ASIC design platform covers all aspects from design to production, offering a comprehensive solution with the latest industry technologies such as MLink, UCIe’s Die-to-Die Interface, InFO, CoWoS, Hybrid CoWoS advanced packaging technologies, PCIe high-speed transmission interfaces, and integrated thermals and mechanical design.

“The emergence of Generative AI has resulted in significant demand not only for higher memory bandwidth and capacity, but also for higher I/O density and speeds, integration of electrical and optical I/O is the latest technology that allows MediaTek to deliver the most flexible leading edge data center ASIC solutions.” said Jerry Yu, Senior Vice President at MediaTek.

As per Economy Daily News citing Industry sources, they have predicted that as the next-generation of optical communication transitions to 800G transmission speeds, the physical limitations of materials will necessitate the use of optical signals instead of electronic signals to achieve high-speed data transmission. This, reportedly, will lead to a rising demand for CPOs with optical-to-electrical conversion capabilities, becoming one of the new focal points for semiconductor manufacturers to target.

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(Photo credit: MediaTek)