[News] Qualcomm Reportedly Enlists Samsung, SK hynix as HBC Memory Partners; TSMC Eyes Packaging Role

Chipmakers are increasingly moving into the memory space, with Qualcomm among the latest to enter the field. The company unveiled its high-bandwidth compute (HBC) architecture in June, separating the compute engine from the SoC and placing it beneath an LPDDR DRAM stack.

Notably, Samsung Electronics and SK hynix, according to The Elec, are now joining Qualcomm’s HBC push. Citing Qualcomm executive vice president Durga Malladi’s remarks at the Deutsche Bank Technology Conference 2026 on Aug. 26, the report suggests that the two Korean memory makers are actively working with Qualcomm to commercialize HBC.

Malladi said he met with the two memory makers in South Korea shortly after Qualcomm’s Investor Day, expecting them to push back on HBC, according to an Investing.com transcript. Instead, both responded positively and signaled a willingness to deepen cooperation with Qualcomm.

The Elec adds that Samsung and SK hynix are developing HBC alongside their existing HBM roadmaps, with Qualcomm set to ship its first-generation HBC product next year. Malladi also said Qualcomm is working closely with both memory makers to secure stable DRAM supplies during the ramp-up.

The HBC ecosystem also brings TSMC into the picture, with each partner taking on a distinct role. Qualcomm will handle the core design and system integration, developing the compute die beneath the DRAM stack and providing the TSV design. Samsung Electronics and SK hynix will be responsible for DRAM stacking, while TSMC is expected to support technology integration and advanced packaging, according to The Elec.

HBC Architecture, Performance and Roadmap

The Elec explains that HBC stacks multiple low-power DRAM (LPDDR) chips vertically and places them directly on top of an accelerator chip (XPU), which serves as the compute die at the bottom of the stack. Through-silicon vias (TSVs) link the HBC accelerator directly to the LPDDR stack, enabling high bandwidth and capacity while avoiding the cost of HBM and advanced packaging, Tom’s Hardware notes.

Qualcomm has not disclosed HBC’s actual bandwidth. However, The Elec reports that while current AI accelerators offer combined HBM bandwidth of around 21–24 TB/s, HBC is claimed to deliver six times the bandwidth and token-throughput efficiency of HBM at the same power consumption.

The architecture is also said to deliver up to 8X the token throughput of conventional GPU systems at the same power, while offering a lower total cost of ownership (TCO) than SRAM, despite SRAM’s higher speed than conventional DRAM.

Qualcomm is already mapping out a rapid HBC rollout. First-generation HBC will debut in the AI250 next year, delivering 18X the bandwidth of the AI200, while the AI300 will follow in 2028 with second-generation HBC and 54X the AI200’s bandwidth. The AI200, due later this year, will use LPDDR5X and provide 43 TB of RAM per rack, according to TechPowerUp.

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(Photo credit: Qualcomm)