[News] Samsung Reportedly Produces Sub-10nm 10a DRAM Working Die Using 4F Square, VCT, Targets 2028 Production

DRAM scaling is becoming increasingly complex as the industry moves deeper into advanced process nodes below 10nm-class levels. The Elec reports that Samsung produced wafers using its 10a DRAM process in March and confirmed a working die during device characterization testing. Notably, this marks the first implementation of a 4F square cell structure and a Vertical Channel Transistor (VCT) process, the report adds.

According to The Elec, Samsung plans to complete development of 10a DRAM using this structure in 2026, followed by quality testing in 2027, and transfer to mass production lines in 2028.

The company is also expected to apply the 4F square cell and VCT structures across three generations—10a, 10b, and 10c, the report suggests, adding that from 10d onward, it plans to transition to 3D DRAM.

The Elec explains that in terms of DRAM, process generations in the 10nm-class node have been labeled sequentially as 1x, 1y, 1z, 1a, 1b, 1c, and 1d. The 10a process corresponds to the next generation after 1d and is considered the first node below the 10nm class, the report notes, adding that industry experts estimate that the actual circuit linewidth is in the 9.5–9.7nm range.

Materials Emerge as Key Challenge for VCT and 4F Scaling

As previously reported by The Bell, current commercial DRAM is based on a 6F square structure, where “F” refers to the minimum lithography feature size in semiconductor manufacturing. The next-generation 4F square design, as per the report, places each cell within a 2F × 2F footprint, enabling higher cell density within the same area as a more advanced scaling approach. The Elec notes that switching to a 4F square structure could increase cell density by around 30–50% within the same die area.

As explained by The Elec, the 4F structure is enabled by VCT technology, in which the charge-storing capacitor is stacked directly above the transistor, allowing tighter cell scaling. Meanwhile, peripheral circuits, which were traditionally located around the cell array, are expected to be built on a separate wafer. These wafers would then be integrated via wafer-to-wafer hybrid bonding under a PUC (Periphery Under Cell) scheme, according to The Elec.

Key challenges stem from material changes required by the introduction of 4F square and VCT technologies. According to The Elec, the channel material has been shifted from silicon to indium gallium zinc oxide (IGZO), which helps reduce leakage current in highly scaled cells and improve data retention, while the word line material is still under evaluation by Samsung.

Notably, Samsung had initially planned to replace titanium nitride (TiN) with molybdenum (Mo) due to its lower resistance and ability to eliminate the need for a barrier layer, the report suggests. However, molybdenum presents processing challenges, including corrosiveness and solid-state handling issues, which would require modifications to gas delivery systems, piping, and process control, the report adds.

SK hynix’s 4F Square and VCT Plans

Other memory giants are also speeding up the development of 4F square and VCT technologies. The Elec notes that SK hynix is reportedly planning to apply 4F square and VCT technologies at the 10b node rather than 10a.

However, The Bell also highlights that the 4F Square Vertical Gate platform requires peripheral wafers to be produced using logic processes. As SK hynix does not have an in-house 12-inch logic line, it is reportedly weighing the trade-off between building internal capability and outsourcing to external foundries, as reliance on partners such as TSMC is also limited by capacity.

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(Photo credit: Samsung)