[News] JEDEC Previews LPDDR6 Enhancements, Develops SOCAMM2 Standard for AI Memory

Amid surging AI and edge computing demand, memory standards continue to evolve at pace. In a recent release, JEDEC Solid State Technology Association revealed new features under consideration for the next revision of its JESD209-6 LPDDR6 standard, while also confirming that an LPDDR6-based SOCAMM2 (System On Chip Advanced Memory Module) specification is currently in development.

According to JEDEC, the upcoming LPDDR6 revision will introduce a narrower per-die interface, including new x12 and x6 sub-channel modes under a non-binary architecture (expanding from x16 to x24). This enables more dies per package and significantly boosts per-channel capacity to meet AI-scale memory requirements.

The standard will also incorporate a flexible metadata carve-out mechanism, designed to preserve peak bandwidth while allowing data center operators to balance usable capacity against reliability needs.

In parallel, LPDDR6 is expected to push memory density toward 512GB—surpassing current LPDDR5/5X limits and better aligning with the growing demands of AI training and inference workloads.

Notably, as NVIDIA is speeding up SOCAMM2 adoption in its Vera Rubin platform, a LPDDR6-based SOCAMM2 module standard is also under development, designed to carry forward the compact, serviceable form factor while providing a clear upgrade path from today’s LPDDR5X SOCAMM2 modules, as highlighted by JEDEC.

On the other hand, JEDEC is close to finalizing an LPDDR6 Processing-in-Memory (PIM) standard, which integrates compute functions directly into memory, reducing data movement between memory and processor, and is aimed at improving inference performance and energy efficiency for both edge and data center workloads.

Samsung, SK hynix Move on LPDDR6 Development

Samsung is emerging as one of the fastest-moving players in the race to commercialize LPDDR6. According to earlier reporting by Wccftech, Samsung has completed development of its LPDDR6 memory and is preparing to move into mass production ahead of a targeted launch in the second half of 2026. Built on its 12nm process, the initial LPDDR6 specification is expected to reach speeds of up to 10.7 Gbps while delivering a 21% improvement in power efficiency over LPDDR5, the report noted, adding further iterations are likely to push data rates beyond 14.4 Gbps.

Another report from The Bell, meanwhile, suggests Samsung has even shipped LPDDR6X samples to Qualcomm, which is expected to adopt them in its upcoming “AI250” AI accelerator.

SK hynix, on the other hand, announced in March that it had successfully developed LPDDR6 based on its 1c process node, achieving speeds of up to 10.7 Gbps, and is targeting mass production readiness in the first half of 2026 with shipments to follow in the second half.

Compared with LPDDR5X, the new generation delivers roughly a 33% uplift in data processing performance, supported by expanded bandwidth and higher throughput. At the same time, power consumption is reduced by more than 20%, enabled by a sub-channel architecture and DVFS technology.

Read more

• [News] SK hynix, Samsung Showcase LPDDR6 at ISSCC as Qualcomm Reportedly Eyes Samsung’s LPDDR6X
• [News] SK hynix Develops 1c LPDDR6 DRAM with 33% Speed Gain, 20% Power Savings; Ships in 2H26

(Photo credit: SK hynix)