[News] TSMC’s 5.5-Reticle CoWoS Reportedly Tops 99% Yield; Flags Memory, ABF as AI Bottlenecks

Amid surging demand for advanced packaging, TSMC Vice President of Advanced Packaging Technology and Services Jun He highlighted the company’s latest CoWoS advances at the 2026 OCP APAC Summit today. According to TechNews and the Economic Daily News, TSMC’s 5.5-reticle-size CoWoS is now in volume production, with yields consistently topping 98% across multiple AI customer products and reaching as high as 99% in some cases.

TSMC is already mapping out its next leap. He said the company expects CoWoS to scale beyond 14× reticle size by 2029, echoing the roadmap TSMC unveiled at its 2026 North America Technology Symposium. TSMC said at the forum that a 14-reticle-size CoWoS package, capable of integrating around 10 large compute dies and 20 HBM stacks, is slated for production in 2028, followed by a move beyond 14 reticles in 2029.

In comparison, Intel notes that its EMIB-T enables systems with a total area exceeding 6x the reticle size today, scaling greater than 8x the reticle size this year and more than 12x by 2028.

The push is also backed by a rapid capacity ramp. Calling himself “the CoWoS guy,” He said TSMC has nearly doubled CoWoS capacity each year over the past three years. The foundry now operates 10 advanced packaging facilities, with capacity steadily catching up with customer demand, according to Economic Daily News. “We haven’t fully met demand yet, but we’re getting very close,” He said.

SoIC Advances Toward 4.5µm Pitch

Meanwhile, TSMC is also speeding up its SoIC (System-on-Integrated-Chips) efforts. According to TechNews, TSMC’s SoIC hybrid bonding enables more than 50× higher interconnect density and 5× greater energy efficiency, with the pitch reaching 6µm in 2025 and narrowing further to 4.5µm by 2029.

As earlier stated by the company, it is also offering its TSMC-SoIC 3D chip stacking technology on its most advanced technology platform, with A14-to-A14 SoIC set to be available for production in 2029, which will provide 1.8X higher die-to-die I/O density compared with N2-on-N2 SoIC.

AI Bottlenecks Highlighted: Memory and ABF Substrates

Notably, according to Next Apple, He also identified memory and ABF substrates as key bottlenecks in the AI supply chain, adding that the industry is likely to face not only memory shortages but also tight ABF substrate supply over the next few years.

As capacity tightens, procurement teams are turning to multiple sourcing to secure supply, but variations in suppliers’ mechanical and thermal properties are making process control more challenging, further complicating manufacturing, he added.

Thus, TechNews, citing He, reports that TSMC plans to set validation scopes and system boundary conditions one year before mass production. Six quarters ahead of production, it will publish the conditions for industry feedback and bring system integrators, equipment makers, and materials suppliers into the parallel development process, enabling faster validation and response to issues.

According to Next Apple, TSMC said early collaboration with suppliers and system integrators, combined with system-level validation and data feedback, can accelerate 3D IC development. For CoWoS, this approach has cut the development cycle from roughly two years per generation to one year, shortening the overall timeline by up to three quarters, the report notes.

Read more

• [News] TSMC CoWoS Supply-Demand Gap Reportedly Seen Narrowing from 20% to 10% by End-2026
• [News] TSMC Reportedly Expands Outsourcing of Key CoWoS Front-End Step to OSATs Amid Rising NVIDIA, ASIC Demand

(Photo credit: TSMC)