[News] HBM Market Heats Up as Three Giants Clash, with HBM4 at the Center

Micron Discusses HBM and Advanced Packaging in the AI Era

Recently, Yulin Chang, Vice President of Advanced Packaging and Testing Operations at Micron Taiwan, outlined the development of HBM and advanced packaging in the AI era. Chang noted that in the past, GPU was connected to GDDR6 via PCB. Today, to achieve peak performance, GPU and HBM memory are integrated on advanced 2.5D/3D packaging platforms such as CoWoS or EMIB. This architecture ensures the shortest data transmission paths and enhanced parallel computing, while delivering major improvements in thermal management and stability. From early 4-layer stacks to today’s popular 8-, 12-, and even 16-layer HBM3, the market’s demand for memory capacity continues to push stacking technology to new limits.

Chang highlighted that while a 12-inch wafer is roughly 775 microns thick, a single HBM3 or HBM4 die is less than one percent of that thickness. Handling such ultra-thin and fragile chips is like constructing precision architecture on paper—but it also opens vast opportunities for innovation. From HBM2E to HBM3, pitch size has shrunk by more than half, while TSV counts have quadrupled. These advances underpin AI’s explosive performance gains, though they also pose steep challenges for packaging engineers.

Among competing packaging approaches, Micron remains one of the few companies committed to a TCB+NCF process. According to Chang, Micron aims to deliver a comprehensive suite of memory solutions to meet the massive data demands of AI training and inference, positioning itself as an indispensable player in the ongoing AI-driven memory revolution.

Samsung to Expand Capacity for Next-Gen HBM

South Korean media reports indicate that Samsung is accelerating construction at its Pyeongtaek Plant 5 (P5), aiming to secure first-mover capacity in next-generation HBM. Workers on-site have begun moving steel structures and undergoing safety training, signaling the imminent resumption of full-scale construction. Samsung plans to restart investment and groundbreaking as early as next month.

Through P5, Samsung seeks to expand its HBM supply capability. Industry observers note that the company could soon supply NVIDIA with fifth-generation HBM3E, before ramping into sixth-generation HBM4. P5 will house a 10nm-class (1c) DRAM line, which Samsung intends to leverage for HBM4 mass production.

NVIDIA is expected to complete HBM4 qualification by Q1 2026 and finalize suppliers and Rubin-series order volumes in the second half of the year. In response, memory makers are racing to strengthen their HBM4 roadmaps.

HBM4 Market Landscape: A Three-Way Showdown

JEDEC officially released the JESD270-4 High Bandwidth Memory (HBM4) standard in April 2025, introducing multiple breakthrough innovations. These include doubling interface width from 1,024 bits in HBM3/HBM3E to 2,048 bits, increasing stack channel count from 16 to 32 (each split into two pseudo-channels), and supporting 4- to 16-high stack configurations with 24Gb or 32Gb dies.

The HBM4 race is now dominated by the “big three”: SK hynix, Samsung, and Micron.

SK hynix shipped the world’s first 12-high HBM4 samples in March 2025 and plans to begin mass production in the second half of 2026.

Samsung has completed HBM4 logic die design and is focusing on custom solutions, reportedly co-developing HBM4 for Microsoft and Meta’s in-house AI accelerators. The company targets HBM4 mass production in late 2025.

Micron has also delivered 12-high HBM4 samples to key customers and aims to start volume production in 2026. The company is positioning its HBM4 with superior energy efficiency and scalability.

With demand surging, TrendForce projects HBM shipments will surpass 30 billion Gb by 2026, with HBM4’s market share steadily rising as suppliers ramp output. By the second half of 2026, HBM4 is expected to overtake HBM3E as the mainstream standard. SK hynix is forecast to retain over 50% share and lead the market, while Samsung and Micron’s performance will hinge on improvements in yield and capacity.

(Photo credit: SK hynix)