[News] Samsung Reportedly Targets 2026 CXL 3.2 Mass Production; SK hynix Advances New AI Memory Architecture

As HBM and DDR approach their capacity limits for AI workloads, leading memory makers are turning to new technologies. According to Seoul Economic Daily, Samsung Electronics and SK hynix are each developing Compute Express Link (CXL) technologies to create a new memory tier for AI systems. HBM and DDR must be directly connected to GPUs and CPUs, limiting memory capacity expansion. By contrast, CXL memory provides a separate memory tier that expands capacity at a relatively low cost without requiring additional GPUs or CPUs, the report notes.

CXL Moves Toward Commercialization

Notably, according to Sharing Economy News, Samsung Electronics plans to mass-produce its CXL Memory Module-DRAM (CMM-D) 3.0, based on the latest CXL 3.2 specification, by the end of this year. Samsung Electronics said CXL memory can increase total memory capacity by up to 50% and double memory bandwidth compared with systems using only DDR5 memory. The technology also supports memory pooling, allowing multiple servers to dynamically share memory resources as needed, the report notes.

The CXL 3.2 specification introduces the Hot Page Monitoring Unit (CHMU), which monitors data access frequency in real time and intelligently places frequently and infrequently accessed data in the most suitable memory locations. By reducing unnecessary data movement, it improves overall memory resource utilization, as noted by Sharing Economy News.

SK hynix Proposes a New CXL Memory Architecture

Sharing Economy News reports that SK hynix showcased samples of its second-generation CMM-DDR5, based on the CXL 3.2 specification, at HPED 2026 last month. The company has entered supply discussions with customers but has not disclosed a mass production timeline. Separately, Seoul Economic Daily reports that SK hynix recently introduced its Inference Memory Tiering Expansion (IMTE) architecture, which improves AI inference efficiency by 35.7% over conventional systems by placing CXL hybrid memory between HBM/DDR and SSD. The architecture creates a new memory tier that combines multi-terabyte capacity with relatively high performance, using CXL as an intelligent hub to coordinate HBM, DDR, and SSD through proactive data movement.

Meanwhile, Micron introduced its CXL 2.0 memory product, CZ120, in 2023 and is reportedly accelerating development of next-generation products based on CXL 3.1 and CXL 3.2, according to Seoul Economic Daily.

Challenges to Broad CXL Adoption

The shift is also gaining support across the broader ecosystem. NVIDIA, Intel, and AMD are incorporating CXL memory support into next-generation chips, including NVIDIA’s Vera Rubin, scheduled for release in the second half of the year, the Seoul Economic Daily report says. Microsoft also reportedly launched a pilot cloud service using CXL memory late last year to improve server efficiency.

However, Sharing Economy News notes that several challenges remain before the CXL market can scale. CPUs, switches, memory controllers, and software must all support CXL, while interoperability between hardware from different vendors must be validated across customers’ production server environments.

The CXL ecosystem is expected to drive greater specialization across the supply chain, according to Sharing Economy News, with memory manufacturers focusing on DRAM production and module development, while fabless companies concentrate on designing CXL controllers and switches. As CXL adoption expands, the benefits are expected to extend beyond memory makers to controller, switch, server, and software companies.

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(Photo credit: Samsung)