[News] TSMC Eyes Chip-Level Microchannel Cooling as AI System Power Could Rise 6× in Five Years

As AI chip power consumption rises rapidly, liquid cooling is becoming increasingly important. According to Anue, TSMC Advanced Packaging R&D Director James Chen said at SEMICON Taiwan 2026 that as AI computing performance continues to increase, total system power could rise around sixfold over the next five years. Power delivery and thermal management are therefore becoming two key challenges for the continued scaling of next-generation AI systems.

Chen said that between 2024 and 2029, CoWoS package size is expected to expand from 3.3 times the reticle size to more than 14 times, while the scale of compute transistors within a single package could increase around 48-fold, Anue notes. Over the same period, total HBM bandwidth per package is projected to grow more than 34-fold, supported by roughly twice as many I/Os and around a sixfold increase in transfer speed per I/O. As Anue highlights, Chen also illustrated the growing power challenge with a projection showing package power rising from around 600W to 4,100W, while power delivery losses could increase more than fivefold.

To address the growing thermal challenge, Chen said the industry is accelerating its shift from air to liquid cooling. Current liquid-cooling designs typically place a cold plate on top of the chip package, with thermal interface materials (TIMs) between the heat source and the cooling system, Commercial Times notes. The next step is to integrate microchannels into the package lid, shortening the heat-transfer path. The industry is also exploring more advanced approaches, including jet impingement and two-phase boiling.

Reducing the interfaces between the chip and coolant is a longer-term goal. Chen noted that while TIMs help fill gaps between the chip, lid, and cold plate, they also add thermal resistance. The ideal long-term direction is therefore to shorten or even eliminate these interfaces and integrate cooling directly with the package or chip structure, Anue notes.

Microchannel cooling is emerging as one approach toward that goal. TSMC has included the technology in its R&D roadmap and is working toward integrating it with advanced packaging, according to Economic Daily News. Microchannel cooling uses tiny fluid channels within the chip or package structure, allowing coolant to absorb and remove heat more efficiently. However, forming channels in the chip for coolant to flow through poses significant manufacturing and packaging challenges, as even a small mistake could render an expensive chip unusable, Economic Daily News adds.

Thermal Management Moves Into Advanced Packaging

Beyond cooling technology itself, TSMC is also co-optimizing packaging, materials, and chip design to improve thermal performance, reducing thermal resistance by up to around 40%, Commercial Times indicates. The report adds that thermal considerations, including package structure, materials, and chip hotspot placement, need to be incorporated early in the design process.

The shift could also raise requirements across the liquid-cooling supply chain. As power consumption per AI rack rises and liquid-cooling systems become more complex, specifications and demand for key components—including cold plates, manifolds, quick-disconnect couplings, coolant distribution units (CDUs), and heat exchangers—are expected to rise accordingly, Commercial Times notes.

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(Photo credit: TSMC)