[News] Samsung Showcases zHBM at FMS 2026, a Next-Gen 3D Memory Architecture with 8X HBM5 Performance
While SK hynix recently unveiled the HBF (High Bandwidth Flash) standard with SanDisk, Samsung is set to showcase its 3D memory and storage roadmap at FMS 2026 as well, highlighting technologies such as “zHBM” and “Z-NAND” aimed at alleviating AI system bottlenecks, according to Money Today.
As noted by the report, at FMS (Future of Memory and Storage) 2026, the world’s largest memory and storage conference during Aug. 4–6, Samsung’s “zHBM” is expected to take center stage as the successor to last year’s z-NAND.
In Samsung’s latest press release, it said next-generation interface system incorporating zHBM is expected to deliver approximately eight times the performance of HBM5. With next-generation wafer bonding technology, zHBM can achieve more than 10 times the memory density of HBM5 while enhancing energy efficiency threefold and reducing thermal resistance by more than half,
The concept of zHBM was first flagged in February at SEMICON Korea. According to a previous ZDNet report, Samsung’s zHBM is a future memory architecture designed to succeed HBM4, which features more than 4x higher bandwidth and 75% lower power consumption compared with next-generation HBM solutions.
Citing Song Jae-hyuk, CTO of Samsung Electronics, ZDNet noted that unlike conventional planar designs, zHBM aims to achieve a fully 3D-stacked architecture by leveraging multi-wafer-to-wafer bonding technology, designed to support tens of thousands of I/O (input/output) connections. Money Today adds that zHBM vertically stacks HBM directly on top of the GPU, replacing the conventional side-by-side layout to minimize data travel distance while significantly boosting bandwidth and power efficiency.
Z-NAND Makes a Comeback for AI Workloads
In the NAND segment, Z-NAND is emerging as a key next-generation strategic product for Samsung, MoneyToday reports. While data stored on SSDs had to pass through the CPU and DRAM before being accessed by GPUs, creating latency bottlenecks, Z-NAND is designed to address this limitation by minimizing latency and boosting I/O (input/output) performance, the report notes.
According to a previous Tom’s Hardware report, Samsung has revived its Z-NAND ambitions in 2025, as the company’s Memory’s executive vice president reportedly said it aims to achieve up to a 15-fold performance improvement with Z-NAND while reducing power consumption by as much as 80% versus conventional NAND flash memory.
However, commercialization challenges remain. According to a previous Global Economic report, Samsung’s Z-NAND previously gained attention for its ultra-low latency and high endurance (DWPD), but its SLC-based architecture also created structural challenges, including higher cost per gigabyte and lower storage density, limiting broader adoption.
According to TrendForce, Z-NAND could deliver ultra-low latency with read speeds approaching DRAM levels. However, its commercialization will depend on overcoming a key hurdle: costs estimated at 3–4 times that of conventional TLC NAND.
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(Photo credit: Samsung)
