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[News] Intel Unveils Xeon 6+ Clearwater Forest at MWC with 18A Chiplet Design and Foveros Direct 3D


2026-03-03 Semiconductors editor

Just weeks after unveiling Panther Lake at CES in January, Intel returned to the spotlight at MWC 2026 with the Xeon 6+ “Clearwater Forest,” showcasing the progress of 18A. According to TechPowerUp, the processor features one of Intel‘s most advanced chiplet designs yet: the package combines 12 compute chiplets manufactured on the Intel 18A node with three active base tiles on Intel 3 and two I/O tiles on Intel 7.

VideoCardz.com reports that Intel positions Xeon 6+ under its “AI-ready network” initiative at MWC, highlighting live-network AI inference and the shift from 5G to 6G. Wccftech, on the other hand, suggests the Clearwater Forest family could hit the market by 2027.

Notably, the Clearwater Forest design links core clusters via a high-bandwidth on-chip fabric, uses Foveros Direct 3D for die stacking, and relies on EMIB for 2.5D interconnects across tiles, according to TechPowerUp.

As previously highlighted by Wccftech, Clearwater Forest is not only fabricated with 18A but also marks Intel’s first high-volume CPU to adopt Foveros Direct 3D, an advanced packaging tech that links compute and I/O tiles through the active base tiles. The solution reportedly features a 9µm bump pitch with copper-to-copper (Cu-to-Cu) bonding, effectively functioning as an active silicon interposer with high density and low resistance.

More Spec Details

TechPowerUp further explains that in Clearwater Forest’s setup, each compute tile houses six clusters of four “Darkmont” efficiency cores, delivering 24 E-cores per tile and up to 288 cores per socket.

For memory and cache, VideoCardz.com highlights that each base tile of Clearwater Forest carries 192 MB of last-level cache, while each compute tile adds 48 MB, along with four DDR5 memory channels per base tile. Another overview slide cited by the report confirms the platform’s key targets: 12‑channel DDR5‑8000 support, up to 576 MB of LLC, 96 PCIe Gen 5 lanes, 64 CXL lanes, and both single- and dual-socket configurations.

According to Ericsson’s internal testing cited by Wccftech, a single 288-core Xeon 6990E+ “Clearwater Forest” processor delivers a 38% drop in rack-level runtime power, over 60% higher performance per watt, and roughly 30% greater overall performance compared with a dual-socket Xeon 6780E “Sierra Forest” system configured with the same 288 cores.

Wccftech notes that the Clearwater Forest architecture increases core density even as it reduces power draw, translating into tangible total cost of ownership (TCO) benefits.

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(Photo credit: Intel)

Please note that this article cites information from TechPowerUpVideoCardz.com, Wccftech and Intel.


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