[News] Samsung Reportedly Targets HBM4E Power Bottleneck with Design Overhaul, Cuts Defects 97%

In the HBM industry, performance metrics such as speed and stack count typically draw the most attention, but power efficiency is emerging as an equally critical factor. According to Hankyung, as the industry transitions to HBM4E, Samsung is proposing a structural redesign of the HBM4 power network.

As the report notes, Samsung is expected to introduce a revamped power delivery architecture starting with HBM4E mass production this year. The approach involves segmenting and redistributing the internal power network, effectively amounting to a structural overhaul.

Power delivery is emerging as the key bottleneck in next-generation HBM. According to the report, citing materials from Samsung, as designs move from HBM4 to HBM4E, the number of power bumps increases from 13,682 to 14,457, requiring thinner and denser wiring within the same space. This raises current density and resistance, leading to greater IR drop, where voltage weakens as it travels through the network.

The resulting heat further increases resistance, exacerbating the cycle and ultimately risking performance degradation or even circuit failure. As a result, designing a highly efficient and well-structured Power Delivery Network (PDN) is emerging as one of the most critical challenges for the HBM industry, the report notes.

Samsung Outlines HBM4E Power Network Overhaul to Improve Efficiency and Reliability

The report first outlines structural weaknesses in current HBM designs, including overly complex wiring and a highly centralized power layout. In existing products, the base die power network is concentrated in large, honeycomb-like MET4 blocks near the interposer, while upper-layer wiring narrows as it routes power into the HBM stack. As the report explains, this transition from wide power blocks to narrow paths creates bottlenecks—similar to traffic congestion when lanes merge.

To address these issues, Samsung introduced PDN segmentation. The large MET4 power block is divided into four smaller sections, and upper layers are further segmented to reduce congestion. As the report highlights, the redesigned routing is more direct and efficient, minimizing unnecessary detours from the bumps to their destinations.

Under the new power delivery network, metal circuit defects in HBM4E were reduced by 97% compared with HBM4, while IR drop improved by 41%, Samsung said, according to the report. The lower IR drop expands voltage margins, enabling higher operating speeds and enhancing overall chip reliability.

Samsung Weighs HBM–GPU Separation, Eyes Photonics for High-Speed Links

While the redesigned power network delivers measurable improvements, the report suggests Samsung is already looking beyond incremental fixes. What if distributed PDNs ultimately reach their limits and thermal challenges in AI semiconductors persist? In response, Samsung points to the concept of disaggregation—physically separating HBM from the GPU.

As the report notes, Samsung is considering photonic interconnects to link HBM and the GPU, enabling physical separation without sacrificing speed. Unlike copper wiring, which operates at gigabit-per-second (10⁹) levels, photonics uses optical transmission that could theoretically reach terabit-per-second (10¹²) speeds—around 1,000 times faster—helping offset latency even if the two components are placed farther apart.

The report adds that Samsung also suggested advances in substrate wiring technology alone could enable physical separation between HBM and the GPU. Currently positioned in near contact, the HBM and GPU could be spaced more than 5 cm apart to help mitigate thermal issues.

Read more

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(Photo credit: Samsung)