[News] Samsung Reportedly Plans MPW Expansion to 2nm in 2027, Unveils 18-Run Program Across Nodes

As Samsung accelerates efforts to secure 2nm customers, it is taking the next step in its MPW strategy. Citing Samsung Foundry Executive Director Song Tae-jung, ZDNet reports that the company’s MPW services are expected to extend to the 2nm node in 2027.

iNews24 notes this is the first time Samsung has officially disclosed a 2nm MPW plan. The company is currently ramping up mass production of its first-generation 2nm process (SF2), while targeting broader applications in HPC, AI, and automotive semiconductors, the report adds.

As explained by the report, MPW (multi-project wafer) allows multiple chip designs from different companies to be fabricated on a single wafer, helping fabless firms cut prototyping costs and validate mass production readiness.

Samsung’s MPW Plan in Detail

ZDNet further notes that Samsung has been running MPW programs across various nodes every year. In 2024 and 2025, the most advanced node offered under MPW reached 4nm, as per the report.

According to iNews24, Samsung also unveiled its MPW operating plan for next year. The company will reportedly conduct a total of 18 MPW runs—seven for 2nm and 4nm processes, and 11 for 5–28nm nodes—with the possibility of further expansion.

As previously reported by SeDaily, Samsung has expressed strong confidence in its 2nm progress, with management stating that it is actively in discussions with multiple major AI and HPC customers on collaboration, and expects to deliver tangible results with some of them in the near future.

While already securing 2nm orders from Tesla’s AI5 and AI6, The Information reports that Google is in discussions for Samsung Foundry to produce key components of its 10th-generation TPU. Under the proposed manufacturing model, TSMC would handle the main compute die on its 1.4nm process, while Samsung would be responsible for a 2nm memory I/O die—a critical interface linking the processor to HBM, the report adds.

TSMC’s Early 2nm CyberShuttle Sets Benchmark

In comparison, TSMC has already been offering a similar MPW-based shuttle service under the “CyberShuttle” brand. According to a prior TechNews report, 2nm was added to CyberShuttle back in 2025, making it the company’s first node to adopt GAA (gate-all-around) transistor architecture.

TechNews, citing market estimates, suggested 3nm wafer pricing at around US$20,000, with 2nm expected to rise further to US$24,000–25,000, increasing cost pressure on smaller IC design houses. Against this backdrop, CyberShuttle is said to reduce early tape-out costs by up to 95%, significantly lowering entry barriers for smaller players.

Read more

• [News] Samsung Reportedly in Talks for Google 2nm TPU I/O Die Order; 2028 Mass Production Eyed
• [News] Samsung 2nm Yields Reportedly at ~55%, Below Mass Production Threshold; Qualcomm May Opt for TSMC

(Photo credit: Samsung)