[News] AMD’s Lisa Su Reportedly to Visit TSMC for 2nm Capacity; Unveils US$10B Taiwan AI Packaging Investment

Ahead of COMPUTEX 2026, competition between the two AI chip giants appears to be heating up, with AMD Chair and CEO Lisa Su arriving in Taipei on May 20. According to Commercial Times, Su is moving ahead of NVIDIA CEO Jensen Huang in beginning supply chain engagements. She is set to attend the AI summit on May 22 and, notably, sources say she may also personally meet with TSMC Chairman C.C. Wei to secure capacity for 2nm process technology and advanced packaging.

As the report notes, AMD has in recent years not only aggressively advanced its Instinct AI GPUs, but also strengthened its EPYC server CPU and rack-scale AI system strategies, aiming to compete more directly with NVIDIA in the AI infrastructure market. AMD announced that its next-generation EPYC processor, codenamed “Venice,” has entered production in Taiwan using TSMC’s 2nm process, with future production planned at TSMC’s Arizona fab. Venice is also said to be the industry’s first high-performance computing (HPC) product to enter production on TSMC’s 2nm technology.

AMD also plans to extend TSMC’s 2nm process across its data center CPU roadmap with “Verano,” a 6th Gen EPYC processor. Built for cloud and AI workloads, Verano is expected to advance the EPYC platform with memory innovations including LPDDR, improving CPU performance, bandwidth, and efficiency for increasingly power-constrained applications, according to its press release.

In addition, AMD today announced more than US$10 billion in investments across Taiwan’s ecosystem to deepen strategic partnerships and expand advanced packaging capacity for next-generation AI infrastructure. The company is working with Taiwan-based ASE and SPIL, along with other industry partners, to develop and qualify next-generation wafer-based 2.5D bridge interconnect technology. The EFB architecture is designed to increase interconnect bandwidth and improve power efficiency, supporting “Venice” CPUs. AMD has also achieved a milestone with PTI by qualifying the industry’s first 2.5D panel-based EFB interconnect.

Rising AI server demand is pushing AMD to accelerate efforts to secure advanced process and CoWoS packaging capacity to avoid future AI chip supply constraints. Against this backdrop, institutional investors cited by Commercial Times say that beyond TSMC, OSAT firms including ASE and Powertech, as well as server ODMs and suppliers of cooling, power, connectors, and high-speed interconnects, are expected to benefit from the next wave of AI infrastructure upgrades.

AMD Demonstrates Compact AI System Powered by Unified CPU-GPU-NPU Architecture

As agentic AI gains traction, the focus is shifting from a GPU computing race toward AI inference, elevating the role of CPUs in AI infrastructure. According to Commercial Times, Lisa Su said data centers previously maintained a CPU-to-GPU ratio of roughly 1:4, but growing adoption of AI agents could push that ratio closer to 1:1. AMD has also sharply raised its CPU market outlook. According to Reuters, Su now expects the server CPU addressable market to grow more than 35% annually, exceeding US$120 billion by 2030.

Aside from her visit to Taiwan, Lisa Su had attended the “2026 AMD AI Developer Day” held in Shanghai on May 19. According to another report from Commercial Times, during the event, Su showcased a palm-sized device powered by a Ryzen AI Max processor that can run a 200-billion-parameter large language model offline. The system adopts a unified RAM architecture, with the CPU, GPU, and NPU (neural processing unit) sharing 128GB of memory. Unlike traditional architectures, data no longer needs to be transferred between VRAM and RAM, significantly reducing overhead.

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(Photo credit: AMD)