[News] Rapidus Reportedly Flags U.S. Firms as Potential Customers, IBM and Tenstorrent Lead the Pack

While Japan’s Rapidus reached a major milestone in July, announcing that prototyping for its 2nm gate-all-around (GAA) chips has begun at the IIM-1 foundry in Chitose, Hokkaido, CEO Atsuyoshi Koike, according to Hokkaido Shimbun, identifies U.S. firms IBM and chip-design startup Tenstorrent as the leading prospective customers.

The report suggests that as per Rapidus’ plan, prototypes for customer products will start next year, targeting several U.S. companies. As per Hokkaido Shiumbun, CEO Atsuyoshi Koike also confirmed that Rapidus has applied for government-backed funding to support domestic next-generation semiconductor production.

As noted by Weekly Economist, the transistors Rapidus produced back in July are the same type of 2nm GAA MOSFETs that IBM prototyped on 300mm wafers. To build expertise, the company sent a total of 150 engineers to the U.S. to train on GAA transistors and has been co-developing mass production techniques with IBM, the report adds.

Notably, as Weekly Economist highlights, Rapidus installed over 200 manufacturing tools at its Chitose, Hokkaido plant, including EUV lithography machines, in December 2024. The report further notes that by April 2025, the facility demonstrated EUV-patterned wafers, with the first test lot processed in June, followed by the prototyping of VLSI-scale test chips with GAA transistors in July.

Progress and Challenges Ahead

The company has been showing confidence on its 2nm progress, which aims to enter mass production in 2027. In July, Nikkei reported that Rapidus CEO Atsuyoshi Koike said the company is in talks with 30–40 potential clients, though factory capacity limits prevent taking them all on.

Nikkei, citing Koike, noted that Rapidus isn’t aiming to directly compete with TSMC, yet Wccftech reports the company is developing its advanced 2nm node, ‘2HP,’ expected to match TSMC’s N2 logic density and surpass Intel’s 18A. However, as per TechPowerUp, by 2027, Rapidus is likely to be one or two nodes behind TSMC, and possibly even Intel.

TechPowerUp adds that to differentiate itself, the company is focusing on agility, highlighting a proprietary all-single-wafer process with a turnaround time of just 50 days, compared with about 120 days for the standard batch–single-wafer mix. On the other hand, Hokkaido Shiumbun also notes Rapidus could also be navigating a challenging path, with partner U.S. startup Esperant Technologies reportedly verging on bankruptcy.

Read more

• [News] Rapidus 2HP Reportedly Surpasses Intel 18A Logic Density Impacted by BSPDN, Rivals TSMC
• [News] Rapidus Unveils 2nm Progress: Prototypes Begin, EUV Exposure Done 3 Months after Delivery

(Photo credit: Rapidus)