[News] Intel EMIB-T Push Gains Momentum as TSMC CoWoS Crunch Drives Spillover; Unimicron, ASE Stand to Benefit

TSMC’s advanced packaging capacity remains tight, with CoWoS orders fully booked. According to Economic Daily News, sources say some back-end advanced packaging orders are spilling over to Intel’s Malaysia operations to support shared major customers, breaking with traditional industry practices. The arrangement could help accelerate TSMC’s front-end advanced process shipments, while institutional investors expect shared supply-chain partners, including ASE and substrate suppliers, to benefit.

As the report indicates, back-end advanced packaging capacity has struggled to keep pace with front-end wafer output, prompting expectations that TSMC will welcome additional suppliers providing capacity support. TSMC Chairman C.C. Wei has previously welcomed competitors adding packaging capacity to ease shortages and give customers greater flexibility, noting that such support could ultimately benefit TSMC’s front-end wafer manufacturing business.

Industry analysts point to HBM shipment data as another sign of Intel Malaysia’s potential role. Around US$1.3 billion worth of HBM was reportedly shipped to Malaysia, while shipments to Taiwan fell below US$3 billion. As Intel is believed to be the only player in Malaysia capable of integrating HBM into chips at scale, analysts speculate that its local plants are providing back-end advanced packaging support.

Intel’s EMIB-T Push Creates New Supply-Chain Opportunities

The shift could also create opportunities for related supply-chain partners. The report notes that Unimicron has secured customer commitments and is working with two Japanese suppliers to advance EMIB-T technology toward mass production in 2027.

Unimicron is also expanding ABF substrate capacity for AI GPUs, AI ASICs, and HPC applications. As noted by MoneyDJ, its EMIB collaboration is already underway, with development currently focused on improving yields toward an initial target of around 50%. Wccftech adds that Intel’s EMIB-T package yields are reportedly approaching 90%, while substrate yields remain the key bottleneck.

ASE could also benefit from broader EMIB-T adoption. As noted by Economic Daily News, COO Tien Wu has said that CoWoS, EMIB, and other packaging solutions are not mutually exclusive, with ASE able to procure substrates and provide assembly and final testing for customers adopting Intel’s EMIB-T.

EMIB’s Cost Advantage Meets CoWoS’s Scale Push

According to TrendForce on Substack, TSMC said at the 2026 OCP APAC Summit that its 5.5x-reticle-size CoWoS is now in volume production, with yields consistently exceeding 98% across multiple AI customer products and reaching as high as 99% in some cases. The company expects to scale CoWoS beyond 14x reticle size by 2029.

TrendForce notes that a key architectural difference between Intel’s EMIB and TSMC’s CoWoS lies in their use of silicon interconnects. EMIB embeds silicon bridges directly into the substrate to provide chip-to-chip connections, eliminating the need for the full-size silicon interposer used by CoWoS and thereby offering lower cost potential.

Assuming comparable yield stability, TrendForce adds that Intel’s EMIB architecture could offer a cost advantage over CoWoS by design. In terms of scaling, Intel previously said EMIB-T is expected to exceed 8x reticle size this year and expand beyond 12x by 2028.

Read more

• Advanced Packaging: Market Trends and Outlook
• [News] TSMC Reportedly Develops EMIB-like Packaging with Kinsus to Prevent Potential Customer Shift to Intel

(Photo credit: Intel)