[News] TSMC Says Energy Efficiency Is Emerging as a Higher Priority Than Computing Power in AI Chip Design

Surging AI-driven electricity demand is making energy efficiency, rather than computing performance, the defining constraint on future chip development. According to Reuters, TSMC Senior Vice President of Business Development Kevin Zhang said at a conference in Amsterdam on May 28 that customers, from smartphone makers to AI data center operators, are increasingly prioritizing performance improvements that minimize additional power consumption amid growing concerns over electricity costs and supply.

Reflecting that shift, TSMC expects its A14 generation, due around 2028, to deliver more than 20% higher computing performance while reducing power consumption by up to 30% compared with its current N2 technology, as the report notes.

While improvements in transistor density remain at the core of TSMC’s roadmap, technologies such as advanced packaging, chip stacking, and photonics are becoming increasingly important in driving efficiency gains, Zhang added, according to the report.

Notably, according to Tom’s Hardware, TSMC’s upcoming A13 and A12 process technologies, both targeted for 2029, are not expected to require High-NA EUV lithography tools. Reuters notes that the decision reflects a broader industry shift, as energy-efficiency improvements are becoming a more urgent priority for next-generation AI chips than continued transistor miniaturization.

TSMC’s Kevin Zhang Comments on Huawei’s Tau Scaling Law

Meanwhile, commenting on Huawei’s Tau Scaling Law, which aims to improve performance by accelerating data movement within chips, Zhang, as cited by the report, said the underlying concept has existed in the industry for years and largely relies on tighter integration of components through technologies such as 3D stacking.

Huawei views LogicFolding, based on its Tau Scaling Law, as a potential step beyond traditional 3D chip stacking. However, according to another report from Reuters, analysts say that while stacking more chip layers can increase transistor density, it also raises power density and overheating risks. Manufacturing yields and costs could present additional barriers to adoption.

Huawei’s roadmap also acknowledges these challenges. He Tingbo, president of Huawei’s semiconductor business, said the technology will depend on new semiconductor design tools optimized for folded chip architectures, as well as more effective heat dissipation solutions for devices ranging from smartphones to AI data centers, Reuters notes.

Read more

• [News] Peking Univ. Unveils EDA for Huawei LogicFolding; Kirin 2026 Reportedly Eyes 3nm-Class Performance
• [News] TSMC Latest Roadmap: A12, A13 for 2029 Without High-NA EUV; A16 Volume Production Delayed to 2027

(Photo credit: TSMC)