[News] Peking Univ. Unveils EDA for Huawei LogicFolding; Kirin 2026 Reportedly Eyes 3nm-Class Performance
Peking University has developed chip design tools tailored for Huawei’s new LogicFolding architecture introduced on Monday. According to South China Morning Post, researchers at the university developed a prototype EDA tool tailored for Huawei’s new Tau (τ) Scaling Law and LogicFolding architecture, designed to optimize chip wiring and reduce resistance for faster signal transmission.
Facing U.S. restrictions on advanced lithography, Huawei is pursuing an alternative chip strategy focused on improving signal transmission speed rather than shrinking transistors, the report notes. The company claims to have developed a “true 3D” approach in which modules are no longer fixed to specific dies, unlike conventional “pseudo-3D” designs, according to a press release from Peking University.
As the Peking University press release explains, this design paradigm creates new demands for EDA tools. Traditional 2D design flows, where modules are assigned to specific dies after synthesis and implemented die-by-die using 2D EDA software, are no longer sufficient to fully unlock the architecture’s potential. To support LogicFolding, physical design must optimize the entire 3D structure within a unified framework, including cross-die interconnects and vertical thermal paths.
The Peking University researchers said early testing on open-source, industry-grade chip designs showed the 3D EDA approach reduced total wire length inside chips by 30%, while also improving performance and thermal management compared with conventional design software, according to South China Morning Post.
Meanwhile, as EDA software remains a critical part of the semiconductor supply chain, developing domestic alternatives has become a major priority for Beijing, with the global market still dominated by Western companies such as Synopsys and Cadence, the report adds.
Huawei’s LogicFolding Push Targets Advanced Node-Level Performance
Chinese media outlet Mydrivers highlights that the performance advantages of mainstream 2.5D and 3D advanced packaging are typically closely tied to leading-edge nodes. By contrast, Huawei’s key LogicFolding breakthrough lies in increasing transistor density through design-level innovation, without relying on a more advanced node.
Mydrivers also notes that Huawei’s next-generation Kirin 2026 chip, expected to launch in autumn 2026, could become the world’s first commercial chip to adopt LogicFolding technology. Official test results cited by the report show the Kirin 2026 achieving a 53.5% increase in transistor density over the Kirin 9030 Pro, reaching 238 million transistors per square millimeter. According to the report, this level could theoretically be comparable to Intel 18A and close to first-generation TSMC 3nm technology.
South China Morning Post highlights that Huawei aims to produce chips by 2031 with performance comparable to 1.4nm technology, without relying on Western chipmaking tools restricted under export controls. However, the report also notes that major challenges remain, as mass production of high-end chips based on the LogicFolding architecture will require new solutions across multiple parts of the supply chain.
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(Photo credit: Huawei)
