[News] Only 1nm, Record-Low Power Consumption: Peking University Team Achieves Chip Breakthrough

According to the School of Electronics at Peking University, the university has made a breakthrough in the field of non-volatile memory. The research team led by Qiu Chenguang and Peng Lianmao has successfully scaled the physical gate length of a ferroelectric transistor down to the 1-nanometer limit, creating the smallest and lowest-power ferroelectric transistor reported to date. The advance is expected to provide core device-level support for enhancing computing performance and energy efficiency in next-generation AI chips. The findings were published online in Science Advances.

World’s Lowest-Power Ferroelectric Transistor Developed

 The Qiu–Peng team at Peking University has proposed a novel “nanogate ultra-low-power ferroelectric transistor” architecture for the first time. By ingeniously engineering the device structure of ferroelectric memory and introducing a nanogate-induced electric field concentration effect, the researchers developed a ferroelectric transistor capable of operating at an ultralow voltage of just 0.6V.

The device achieves an energy consumption as low as 0.45 fJ/μm and reduces the physical gate length to the ultimate 1-nanometer limit, making it the smallest and most energy-efficient ferroelectric transistor reported globally. This new physical mechanism-based memory device opens up promising pathways for sub-1-nanometer node chips and high-compute AI chip architectures.

Toward Logic-Compatible, Ultra-Low-Voltage Ferroelectric Memory

Ferroelectric transistors store data through polarization switching in ferroelectric materials, which are regarded as one of the most promising semiconductor memory technologies in the post-Moore era. Leveraging bistable polarization states and a three-terminal transistor structure, they hold strong potential for enabling non-volatile computing-in-memory architectures—effectively integrating storage and high-speed computation. The technology is widely seen as a key solution to overcoming the long-standing “memory wall” bottleneck and advancing AI hardware architectures.

However, conventional ferroelectric transistors have long been constrained by the intrinsic coercive voltage limits of planar ferroelectric materials. In practice, polarization switching and data erase/write operations typically require voltages above 1.5V. Although already more efficient than Flash memory, traditional designs cannot theoretically reduce operating voltages below 0.7V—preventing compatibility with mainstream logic voltage levels. Thus, how to achieve sub-0.7V ultralow-voltage memory operation has become a critical challenge for breaking through memory bottlenecks and enhancing AI chip performance.

Nanogate Structure Breaks the Voltage Barrier

In this research, the Peking University team introduced both a “nanogate ferroelectric transistor structure” and a “nanogate electric field enhancement mechanism.” By aggressively scaling the gate electrode to the nanometer limit, the researchers harnessed the tip-induced electric field concentration effect of the nanogate.

This design creates a highly localized and intensified electric field region within the ferroelectric layer, significantly amplifying local field strength and dramatically lowering the voltage required for polarization switching. The approach surpasses the coercive voltage limits of conventional planar ferroelectrics and overturns the long-standing trade-off between low operating voltage and high coercive electric field.

As a result, the team achieved an ultralow operating voltage of 0.6V—bringing ferroelectric memory voltage down to logic-level compatibility. The fabricated device delivers energy consumption as low as 0.45 fJ/μm, outperforming previously reported international results by an order of magnitude, with storage speeds approaching 1 nanosecond.

Notably, the study is the first worldwide to reveal an anomalous scaling advantage in ferroelectric transistors: as the physical gate length shrinks to the 1-nanometer limit, electric field convergence and enhancement become significantly stronger. The extremely small gate dimension effectively improves ferroelectric memory characteristics, underscoring the substantial potential of ferroelectric memory technologies in future sub-nanometer node chips.

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