[News] China’s Empyrean Reportedly Cuts Chip Design Task from 4 Weeks to One with AI, Eyes New EDA Opening with Tau Law

AI agents are rapidly reshaping chip design—and China is betting on them to accelerate its push for tech self-reliance. According to the South China Morning Post, EDA leader Empyrean Technology has cut a circuit-layout task from four weeks to just one by integrating an AI agent into its simulation and layout tools.

Chairman Liu Weiping, per the report, said Empyrean is using AI-optimized algorithms and autonomous agents to speed up increasingly complex chip development. And the productivity gains are not unique to China. An earlier Chosun Biz report noted that Samsung cut some custom SoC verification tasks from more than a month to just two days using Anthropic’s Claude.

AI Gives China’s EDA Push New Momentum

For China, however, the stakes go beyond faster chip design. EDA software is essential to designing and validating chips before production, yet the global market remains dominated by Western players including Synopsys, Cadence Design Systems and Siemens EDA, the South China Morning Post notes, adding that building homegrown alternatives has therefore become a strategic priority for Beijing.

The shift could go beyond chip design. As agentic EDA takes hold, traditional software licensing could give way to token-based usage, reshaping how EDA tools are sold and consumed, South China Morning Post suggests, noting that Empyrean is betting on that transition with an agentic platform designed to integrate its own AI agents with those from partners.

Empyrean’s push is also part of a broader national strategy. China’s Ministry of Industry and Information Technology (MIIT) last Friday unveiled an action plan calling for deeper integration of AI and software, including critical industrial tools such as EDA and computer-aided design, the South China Morning Post reports. The ambition, according to the report, would be move China toward the high end of the global value chain by 2030.

Tau Law Opens a New Front for China’s Homegrown EDA

Beyond AI, the emerging Tau (τ) Law could open another window of opportunity for China’s homegrown EDA industry—and Empyrean is already building tools around it. According to EE Times China, unlike conventional 3DIC packaging, which integrates relatively independent modules, τ-driven “logic folding” enables deeper restructuring of chip circuitry, which creates new demands for EDA tools.

According to the report, Empyrean is already building native tools around the concept, spanning 3DIC data infrastructure, circuit partitioning, physical implementation and multiphysics analysis. Its end-to-end 3DIC design solution has been deployed in HiSilicon chip projects, while its 3D system-level verification platform has cut tasks that once took two to three months to less than a month, the report suggests.

That push is already translating into broader adoption at HiSilicon. EE Times China, citing HiSilicon CIO Diao Yanqiu, reports that users of a homegrown digital simulator jumped 16X in just one year, while Kunpeng core usage rose nearly 8X.

The momentum extends across HiSilicon’s EDA stack. The number of domestic EDA tool categories deployed at scale climbed from 17 in 2025 to 26 in 2026, according to the report. Most notably, HiSilicon disclosed the homegrown toolset used for its first logic-folding chip project: “τ EDA V0.1,” the report adds.

Read more

• [News] ByteDance Reportedly Develops In-House CPUs Amid Supply Tightness; Explores Both Arm and RISC-V
• [News] Peking Univ. Unveils EDA for Huawei LogicFolding; Kirin 2026 Reportedly Eyes 3nm-Class Performance

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