[News] Huawei Addresses Tau Scaling Heat Concerns as Kirin 2026 Tests Show ~55% Higher Density but Lower Power

Huawei is offering new data to support its chip-scaling approach, suggesting that higher transistor density does not necessarily come at the cost of higher power consumption. According to Global Times, a new paper by Huawei semiconductor segment chief He Tingbo on the company’s Tau (τ) Scaling Law presented measurements from the Kirin 2026 chip, with transistor density increasing by about 55% while power consumption fell across several key computing units at comparable performance.

The paper, titled “Huawei’s τ Chip Was Supposed to Melt?” was recently posted by He on ChinaXiv, a preprint platform operated by the Chinese Academy of Sciences, STAR Market Daily notes. The paper addresses concerns that sharply increasing transistor density through folding could raise power density and make chips run hotter. Kirin 2026 measurements, however, showed power consumption falling 66% for the NPU, 58% for the GPU, and 41% for the CPU performance core at the same performance level, STAR Market Daily highlights. The NPU stood out, maintaining 29 TOPS while operating at a 63% lower frequency and reducing voltage from 0.85V to 0.55V, with power density falling 73%.

LogicFolding Reduces Power by Cutting Data Movement

According to the paper, much of a chip’s energy consumption comes from moving data rather than computation itself. As STAR Market Daily indicates, the Kirin chip reduces this burden by cutting data movement, which accounts for more than 80% of the energy consumed by a SoC module.

LogicFolding tackles this by turning long horizontal interconnects into short vertical connections between stacked layers, significantly shortening signal paths and reducing interconnect capacitance and energy consumption, as noted by EE Times China. Measurements show that typical core routing lengths can be reduced by 20%, with some critical paths shortened by as much as 70%. The Kirin 2026 uses a 1.5-micrometer hybrid-bonding pitch and has around 50 million vertical interconnects, 10–15% of which are used for signal transmission.

The paper also points to further scaling in future generations. Kirin 2027 test silicon has already reduced the hybrid-bonding pitch to 1 micrometer, with more than 100 million vertical interconnects. Over the next three years, Huawei plans to further shrink the pitch to 720nm while increasing the number of vertical interconnects to more than 200 million, EE Times China adds.

LogicFolding May Face Key Engineering Challenges

However, folding is not an ultimate solution and will require continued system-level engineering and iteration. He stressed that Tau is a time-scaling law, not an energy-scaling law: if designers use all the time saved to raise frequency, power consumption could instead increase. STAR Market Daily also notes that major engineering challenges remain, including hybrid-bonding pitch, wafer warpage, alignment accuracy, and EDA tool adaptation, with further work needed in these areas over the next three to five years.

The Kirin 2026 is expected to power Huawei’s Mate 90 flagship series and its second-generation tri-fold smartphone, the Mate XT 2, both set to be unveiled in September, as noted by Commercial Times. The Mate 90 opened for pre-orders on August 31 and is expected to be officially unveiled starting September 7.
Read more

• [News] Huawei Reportedly Readies Mate 90, XT2 for Sept. with Tau Scaling Chips Said to Match 3nm Performance
• [News] Huawei Expands Tau Scaling Law V2 Paper, Highlighting LogicFolding Path to Ascend AI Chips in 2030

(Photo credit: Huawei)