[News] Samsung Files New HBM Dummy Die Patent to Enhance High-Stack Reliability; Seen as Aimed at 16-Layer HBM5
As the industry advances toward higher-layer HBM, Samsung is reportedly developing a new structural design to improve package reliability. According to ETNews, Samsung Electronics has filed a patent targeting reliability issues in high-bandwidth memory (HBM) packaging. With the industry transitioning to higher-layer HBM such as HBM4E and HBM5, the company is redesigning the dummy die that protects the memory stack to improve structural integrity and manufacturing yield.
As detailed in the report, the HBM packaging patent describes a technology that shapes the sidewalls of the topmost dummy die into a three-step terraced structure with a curved profile. The report adds that Samsung is expected to combine the technology with its existing HBM packaging technologies, including hybrid bonding and HPB (Heat Path Block).
Industry sources cited by the report note that in HBM stacks with 12 layers or more, warpage of the topmost dummy die is a key factor affecting manufacturing yield, suggesting the technology is intended for HBM5 products with 16 layers or more.
Why the Dummy Die Matters
As highlighted in the report, improving the dummy die structure helps mitigate warpage and thermal expansion mismatch, two major contributors to yield loss. As HBM stack heights increase beyond 12 layers, the reliability of the topmost dummy die becomes increasingly important, with industry estimates suggesting yields fall by 10–20 percentage points from 8-layer to 12-layer HBM and further to around 40–60% for 16-layer stacks.
The report notes that HBM packages stack multiple memory dies vertically on a base die, with a dummy die at the top of the stack. The dummy die helps maintain the required package height, protects the memory stack, and assists with heat dissipation.
Key Design Innovations
The patent shows that Samsung’s dummy die design utilizes a Deep Groove Sawing process, a high-precision laser dicing technique that creates deep grooves in the wafer to separate individual dies. Compared with conventional mechanical blade sawing, it enables deeper, more precise cuts while reducing damage to the semiconductor crystal structure.
The design also adopts an inverted pyramid profile, with a narrower bonding interface at the bottom and a wider top surface to improve mechanical strength over conventional straight sidewalls. In addition, trenches (Tr) are introduced in the non-bonding region (NBR) before sawing to prevent dicing debris from contaminating the bonding interface, improving the reliability of fusion bonding.
Notably, the report notes that the patent also addresses thermal management. It defines a vertical distance of 1–10 μm between the underside of the bonding insulating layer and the horizontal extension plane to preserve existing heat-transfer efficiency. In addition, the design incorporates a protruding surface that reduces the volume of the epoxy molding compound (EMC), potentially further improving heat dissipation.
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(Photo credit: Samsung)
