[News] Samsung-Backed Vertical Die Research Reportedly Targets 10x I/O and 4x Bandwidth Gains for HBM

Although JEDEC is expected to ease height restrictions for HBM, raising the limit to around 900 micrometers (µm) from 775 µm in HBM4, the industry continues to search for ways to overcome the structural limits of conventional HBM architectures. According to ET News, a “Vertical Die”-based advanced packaging project under Samsung Electronics’s Future Technology Research program is showing tangible progress.

Notably, the report suggests the approach reportedly boosts input/output (I/O) density by up to 10 times and improves bandwidth by roughly fourfold.

ET News reports that the project, led by KAIST professor Kwon Ji-min as principal investigator, has achieved a key academic milestone, with a paper on the Vertical Die architecture accepted for presentation at the 2026 IEEE Symposium on VLSI Technology and Circuits in June, one of the most prestigious global conferences in semiconductor devices and circuit integration.

Vertical Die Architecture Pushes I/O and Bandwidth Limits

One of the project’s main breakthrough lies in its vertical die (V-die) technology, which reorients chips by standing them upright at a 90-degree angle, like books on a shelf, the report explains.

While current HBM stacks DRAM chips vertically and uses through-silicon vias (TSVs) to transmit data between layers, each TSV consumes part of the die area, limiting the ability to significantly increase input/output (I/O) terminals (about 2,048 in HBM4), the report notes, adding that as the stack grows taller, heat dissipation also becomes increasingly difficult.

Instead, this new structure allows the entire long edge of the die to be used as a pad region, significantly expanding the number of I/O connections and enabling much higher bandwidth scalability, according to ET News.

The report, citing Professor Kwon’s team’s research results, suggests that the vertical die architecture can increase the number of input/output (I/O) terminals by 10 times—up to around 20,000—compared with HBM4’s roughly 2,048 I/Os, under the same footprint. Bandwidth is reportedly improved by about fourfold as well, while data read latency is significantly reduced.

Two additional breakthroughs are also highlighted in the report: first, the team fabricated transmission lines by directly electroplating copper onto glass substrates—widely seen as a next-generation packaging material—and successfully validated signal integrity (SI).

Notably, the report also points out that the team is taking a novel approach to thermal management, by proposing a “direct liquid cooling” method that uses the microscopic gaps between chips as channels for coolant flow, enabling more uniform temperature distribution across all layers.

According to Samsung, the V-die integrated packaging technology developed in this study could extend beyond next-generation AI accelerators to a wide range of applications, including ultra-high-speed memory–logic integration, high-performance computing (HPC), and high-frequency communications.

Read more

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(Photo credit: Samsung)