[News] SerDes Wars Heat Up: Broadcom, Marvell, MediaTek Battle for AI Interconnect Supremacy

As AI models expand at breakneck speed, SerDes (Serializer/Deserializer) has become pivotal for boosting chip-to-chip data bandwidth. As observed by TrendForce, competition in high-speed SerDes has been heating up since 2025. In addition to Broadcom and Marvell, MediaTek reportedly broke into Google’s TPU ecosystem with its 224G SerDes, while NVIDIA began opening its NVLink Fusion SerDes IP to IC and IP design partners.

Against this backdrop, SerDes capabilities are becoming a key differentiator for ASIC vendors, as companies race to strengthen interconnect technologies to support AI infrastructure. This raises key questions around what SerDes is, why it has become so critical, and which players are shaping this fast-evolving landscape.

What is SerDes?

36Kr explains that SerDes (Serializer/Deserializer) is a foundational technology enabling high-speed data transfer between chips, designed to maximize bandwidth across chip-to-chip links while minimizing the number of physical I/O connections.

TrendForce notes that SerDes achieves this by converting large volumes of parallel data into high-speed serial streams for transmission (serializer), then restoring them back into parallel data at the receiving end (deserializer). By doing so, the tech significantly boosts data throughput without increasing I/O pins. As 36Kr points out, once just another interface block on a chip, SerDes has been elevated in the AI era to critical infrastructure — a key determinant of how far a system can scale.

ASIC Vendors Compete in the SerDes Arena

TrendForce observes that competition in the high-speed SerDes market centers on two key camps: established SerDes IP vendors such as Synopsys and Cadence, and ASIC design houses developing in-house SerDes capabilities.

36Kr notes that it is no coincidence that leading ASIC design houses, such as Broadcom and Marvell, are also SerDes powerhouses, as the technology ensures reliable chip-to-chip connections. Among them, Broadcom’s data center Tomahawk switches are essentially SerDes density monsters: Tomahawk 5 (51.2T) integrates up to 64 Peregrine SerDes cores, each with eight 106Gbps PAM4 transceivers and PCS, the report adds.

Tomahawk 6, which began shipping in June, introduces a chiplet architecture and supports 100G/200G SerDes along with co-packaged optics (CPO). Designed for AI clusters exceeding one million XPUs, it delivers a comprehensive set of AI routing and interconnect features, and is manufactured on TSMC’s 3nm process, according to Reuters.

On the other hand, 36Kr notes that as Broadcom’s SerDes is renowned for high performance and deep integration, Marvell’s strength lies in protocol breadth and advanced process node adaptability. Notably, the report highlights that Marvell leads Broadcom on PCIe SerDes cadence, giving it a decisive edge in server-side HBM connectivity and storage controller markets.

Marvell is also pushing ahead in the advanced node race, as it unveiled in 2025 its first 2nm silicon IP for next-gen AI and cloud infrastructure, produced on TSMC’s 2nm process. As the company stated, the platform centers on a broad portfolio of semiconductor IP, including electrical and optical SerDes, 2D/3D die-to-die interconnects, advanced packaging, silicon photonics, custom HBM compute architectures, on-chip SRAM, SoC fabrics, and high-speed interfaces like PCIe Gen 7.

MediaTek Rises as a SerDes Contender

Notably, TrendForce notes that MediaTek has emerged as a strong contender, as it has already pushed its SerDes to 200G, with 400G IP projects slated for 2026. According to TrendForce, AI chips are transitioning to 224G SerDes by late 2026 — and MediaTek’s 224G capability is proving central to winning the TPU v8e (Zebrafish) program and beyond.

According to Commercial Times, MediaTek’s foothold in the cloud ASIC market is anchored by its long-standing SerDes expertise: currently, MediaTek’s 112Gb/s SerDes DSP uses a PAM-4 receiver architecture and achieves over 52dB loss compensation on 4nm, maintaining low signal attenuation and high interference immunity—key for data centers and advanced packaging. Its 224G SerDes, designed specifically for data center applications, has completed silicon verification and draws strong industry attention for its technical maturity, the report notes.

However, challenges are emerging for current ASIC players, as TrendForce notes that competition in the SerDes market is intensifying, with 224G SerDes development and optical engine integration becoming key differentiators. Citing remarks from MediaTek’s management, TrendForce suggests that as data rates continue to climb, traditional copper interconnects are hitting physical limits. Thus, beyond 400G, the technology will inevitably move into the optical domain, which represents a key focus for industry players’ future investments.

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(Photo credit: Broadcom)