[News] TSMC’s CoWoS-L/ S Reportedly Fully Booked, OSAT Partners Step up with ASE’s CoWoP in Focus

Amid heightened attention on Intel’s EMIB (Embedded Multi-die Interconnect Bridge), TSMC is experiencing exceptionally strong demand for its own advanced packaging. According to Economic Daily News, a surge of AI and HPC orders from NVIDIA, Google, Amazon, and MediaTek has driven TSMC’s entire CoWoS lineup to full capacity, with both CoWoS-L and CoWoS-S fully booked.

Commercial Times explains that AI GPUs and ASICs are rapidly growing in both complexity and size—from bigger compute dies to HBM stacks rising from six to eight. As this escalation is putting heavy pressure on TSMC’s CoWoS capacity, the Economic Daily News, citing supply chain sources, reports that the foundry giant’s current expansion efforts are centered on CoWoS-L, while CoWoS-S capacity is being boosted through equipment reallocation to relieve bottlenecks.

According to Commercial Times, TSMC’s AP8 facility in Southern Taiwan Science Park and AP7 in Chiayi have begun equipment move-in this quarter. Industry estimates cited by the report note that by the end of 2026, TSMC aims to scale monthly CoWoS capacity from today’s 75,000–80,000 wafers to as high as 120,000–130,000.

OSATs Step Up: From Second Supply Chain to Advanced Packaging

Notably, TSMC’s capacity crunch is creating a spillover effect. Commercial Times reports that the shortage is not only pushing TSMC to accelerate its own expansion but is also fueling the rise of a “TSMC-like” second supply chain centered on OSATs. The foundry giant, as per the report, has already begun outsourcing select products—mainly those with simpler RDL (redistribution layer) structures—to these partners.

The report adds that top-tier customers, wary of depending on a single supplier, are actively developing a second supply chain—benefiting ASE in particular. Equipment sources cited by Commercial Times project ASE’s CoWoS capacity to jump to 20,000–25,000 wafers per month by year-end, more than tripling current output.

It is worth noting that OSAT vendors have already begun moving into the more technically demanding front-end CoW (Chip-on-Wafer) processes, Commercial Times suggests. The Economic Daily News reports that NVIDIA is developing a new packaging technology, CoWoP (Chip-on-Wafer-on-PCB), which could eventually eliminate the substrate. The project is reportedly being led by SPIL, part of ASE Technology Holding, in coordination with several top PCB manufacturers—stirring fresh industry buzz and further elevating ASE’s market profile.

Read more

• [News] TSMC CoWoS Capacity Crunch Reportedly Pushes U.S. AI Chipmakers to Powertech Through 2027
• [News] FOPLP Trial Yields Reportedly Reach 90% at Powertech as TSMC Advances CoPoS Development

(Photo credit: TSMC)