[News] New “Intelligent” Chip Emerges, Expected to Break Computing Energy Bottleneck

Per the latest issue of Nature Electronics, a joint research team including Politecnico di Milano has developed a new type of “intelligent” chip featuring an innovative architectural design that significantly reduces energy consumption while dramatically boosting data processing speed, which is expected to address the long-standing energy efficiency bottleneck in computing.

The research marks an important step toward more compact, efficient, and sustainable computing devices, with broad application prospects across artificial intelligence (AI), large-scale data processing, next-generation wireless communications, as well as robotics, data centers, and 5G/6G networks.

Based on an in-memory computing architecture, the chip excels in overcoming the inefficiencies of traditional computing systems caused by frequent data transfers between memory and processors, which presents as its core strength. By minimizing internal data movement, the design achieves higher energy efficiency and faster processing. The team demonstrated a fully integrated analog accelerator fabricated using standard CMOS technology, capable of solving both linear and nonlinear systems of equations.

The chip integrates two 64×64 programmable resistive memory arrays, with memory cells arranged in a grid. Each cell is built on static random-access memory (SRAM) technology combined with integrated resistors to enable multi-level programmable resistance. It incorporates analog processing components—including operational amplifiers and analog-to-digital converters—forming a novel analog computing architecture.

This design allows complex computational tasks to be executed directly within the memory structure, eliminating the need to transfer data to external processors and thereby significantly reducing computational latency. Experimental results show that, while achieving accuracy comparable to conventional digital systems, the chip delivers lower power consumption, shorter computation times, and a smaller chip footprint.

The research team noted that this integrated chip demonstrates the industrial viability of innovative architectures such as analog computing. The team is now working to advance the technology toward real-world applications, particularly in AI, with the goal of reducing the energy costs of computation.

This work highlights the outcomes of international collaboration between academia and industry, involving universities and research teams from multiple countries, and collectively advancing the development of analog in-memory computing for high-performance, energy-efficient applications.

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