Press Center

DRAM CAPEX of 2009 Decreased by 56%, says DRAMeXchange

17 April 2009 Semiconductors

Taipei, April, 15th, 2009 --- The 2008 DRAM chip price dropped more than 85%, while the global DRAM industry has faced more than two years of cyclical downturn, and the consumer demand suddenly froze because of the global financial crisis in 2H08. In 1Q09, the DDR2 667 MHz 1Gb chip price rebounded to an average of US$ 0.88, which fell between the material cost and cash cost level. Still, the DRAM vendors encountered huge cash outflow pressure. Not only were capacity cut conducted, the process migration schedules were also delayed in the wake of respective sharp CAPEX cuts. According to the survey of DRAMeXchange, the worldwide DRAM CAPEX of 2009 has been revised down to US$ 5.4 billion, sharply down by 56%, in contrast to the US$ 12.2 billion in 2008.

WW DRAM 50 nm Process Migration Schedules All Deferred One to Two Quarters

From the roadmaps of DRAM vendors, the adoption schedule of DRAM mass production using the 50 nm process have now been delayed one to two quarters. DRAMeXchange estimates that by the end of 2009, the DDR3 will account for 30% of the standard DRAM. Regarding the new DDR2 and DDR3 process migration, all DRAM vendors still own different types of strategies of density and types. For example, the Korean vendors’ 50 nm process migration schedules of DDR 3 are earlier than DDR2 and the 2 Gb DDR3 mass production schedule is earlier than the 1Gb chip. As for the U.S. and Japanese vendors, according to their DDR3 roadmap, the 50 nm process will be introduced between 3Q09 and 4Q09, which is later than the Korean vendors, and also firstly with mass production of 2 Gb DDR3. Therefore, in the DDR3 era, the density will mainly be 2 Gb which is a lower cost driver with more stimulating incentive to the market demand of higher density chips. The Taiwanese vendors are under the high cash pressure and are falling behind in the 50 nm process race. They are mainly focused on “pilot production”.

The Gross Die Increases 40% to 50% with 50 nm Process Drives Down the Cost

According to the famous Moore’s Law, the number of transistors on an integrated circuit doubles every 12 months. After the process shrinking became more difficult in the recent decade, it increased to 24 months. With new process migration, the closer the line distance is the larger gross die number a single wafer gets, meanwhile the cost is lower and the vendors gain more competitiveness. The average DRAM output increased about 30% during the process migration from 70 nm to 60 nm. With the improvement of process design and die shrink in the same generation of process technology, the output can once again increase 20%. In the 50 nm generation, the output will increase almost 40% to 50%, compared to 60 nm process and the number of gross die increases to 1500 to 1700 per 12 inch wafer with another 30% cost down.
The Cost of Immersion Lithography Tools is the Major Capital Expenditure of 50 nm Process Migration

The major challenge of 50 nm process migration is the lithography technology. The newest immersion lithography equipment is required and the older exposure equipment at the wavelength of 193 nm is no longer suitable under 65 nm process, due to the physical limitations. Traditional dry lithography uses air as the medium to image through masks. But Immersion lithography uses water as the medium. Immersion lithography puts water between the light source and wafer. The wavelength of light shrinks through water so it is able to project more precise and smaller images on the wafer. This is the invention that enabled the semiconductor process technology to migrate from 65 nm to 45 nm.

The current major immersion equipment vendors are ASML, Nikon, and Canon. The largest vendor in the market is AMSL, which is now mainly promoting its XT1900Gi, a tool that is capable to go lower than 40 nm and is the most accepted model in the industry. Nikon still promotes its NSR-S610C, which was launched in 2007 and is able to go down to 45 nm process. Canon launched its FPA-7000AS7 in mid 2008 that supports the process under 45 nm.

Figure-1 Table of Immersion Equipments

Wafer Size
< 40 nm
> 131 wph
< 45 nm
> 122 wph
≤ 45 nm
≥ 130 wph
≤ 55 nm
≥ 130 wph
< 45 nm
≥ 130 wph

Source: DRAMeXchange, Apr. 2009
From the preliminary estimation, it takes at least US$ 210 million to just upgrade the equipment in this single immersion production line in order to convert a 70 K monthly capacity to immersion technology. With other migration related cost, it might take US$ 100 million CAPEX.

Previous Article
SSD Evaluation List of 1H2009 announced by DRAMeXchange
Next Article
NAND Flash Contract Price of 1H April Rose Due To Shipment Adjustment, states DRAMeXchange

Get in touch with us